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郁悶 端口buffer

作者:gggman 欄目:通信技術(shù)
郁悶 端口buffer
小弟進(jìn)來(lái)做個(gè)小程序 仿真過(guò)不了!
index 是個(gè)buffer端口 通過(guò)查表所得數(shù)值與其做加法運(yùn)算 然后傳給下一級(jí)使用,同時(shí)返回給輸入端,由下一個(gè)輸入再次更新~~
程序如下
--------------------------------------------------------------------

------------
-- Company:
-- ENGINEER:
--
-- Create Date:    22:48:39 05/04/07
-- Design NAME:    
-- MODULE NAME:    kuis_1 - Behavioral
-- Project NAME:   
-- Target DEVICE:  
-- Tool versions:  
-- DESCRIPTION:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------

------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any XILINX primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity kuis_1 is
    PORT ( code : in std_logic_vector(3 downto 0);
           index : buffer std_logic_vector(8 downto 0));
end kuis_1;

architecture Behavioral of kuis_1 is
function adder9
    ( a:std_logic_vector;
     b:std_logic_vector
     )
     return std_logic_vector is
variable vsum : std_logic_vector(8 downto 0);
variable carry : std_logic;
variable i:integer;
begin     

        carry :='0';
        for i in 0 to 8 loop
            vsum(i):= (a(i) xor b(i)) xor carry;
            carry := (a(i) and b(i)) or (carry and (a(i) or b(i)));
        end loop;
          return vsum;
end adder9;
signal tmp:std_logic_vector(8 downto 0);
signal tmp1:std_logic_vector(8 downto 0);
begin
p1:PROCESS(code)
begin
    case code is
        when"0000"=> tmp<="111111111";
        when"0001"=> tmp<="111111111";
        when"0010"=> tmp<="111111111";      
        when"0011"=> tmp<="111111111";     
        when"0100"=> tmp<="000000010";    
        when"0101"=> tmp<="000000100";  
        when"0110"=> tmp<="000000110";
        when"0111"=> tmp<="000001000";
        when"1000"=> tmp<="111111111";        
        when"1001"=> tmp<="111111111";         
        when"1010"=> tmp<="111111111";        
        when"1011"=> tmp<="111111111";        
        when"1100"=> tmp<="000000010";         
        when"1101"=> tmp<="000000100";        
        when"1110"=> tmp<="000000110";        
        when"1111"=> tmp<="000001000";  
        when others=> tmp<="ZZZZZZZZZ";
    end case;
end PROCESS p1;
p2:PROCESS(tmp,index)
begin
tmp1<=adder9(index,tmp);
index<=tmp1;
end PROCESS p2;
end Behavioral;


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