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初學。為什么在FPGA上仿真OK，在CPLD上沒有輸出。
作者：lfk_888　欄目：EDA技術
初學。為什么在FPGA上仿真OK，在CPLD上沒有輸出。
下面這段程序在FPGA和CPLD(EPM7128)上都編譯OK，但在仿真時在FPGA上仿真OK，在CPLD上仿真卻沒有輸出。不知什么原因？請教各位大蝦
MODULE sin_rom(clk,addr,data);
input clk;
input [4:0] addr;
OUTPUT [15:0] data;
reg [15:0] data;

always@(posedge clk)
begin
      case (addr)
  5'h00    : data<=16'hf000;
    5'h01    : data<=16'hf600;
    5'h02    : data<=16'hf900;
    5'h03    : data<=16'hfc00;
    5'h04    : data<=16'hff00;
    5'h05    : data<=16'hcf00;
    5'h06    : data<=16'h9f00;
    5'h07    : data<=16'h6f00;
    5'h08    : data<=16'h0f00;
    
    5'h09    : data<=16'h0f60;
    5'h0a    : data<=16'h0f90;
    5'h0b    : data<=16'h0fc0;
    5'h0c    : data<=16'h0ff0;
    5'h0d    : data<=16'h0cf0;
    5'h0e    : data<=16'h0af0;
    5'h0f    : data<=16'h06f0;
    5'h10    : data<=16'h00f0;
    5'h11    : data<=16'h00f6;
    
    5'h12    : data<=16'h00f9;
    5'h13    : data<=16'h00fc;
    5'h14    : data<=16'h00ff;
    5'h15    : data<=16'h00cf;
    5'h16    : data<=16'h009f;
    5'h17    : data<=16'h006f;
    5'h18    : data<=16'h000f;
    5'h19    : data<=16'h600f;
    5'h1a    : data<=16'h900f;
    5'h1b    : data<=16'hc00f;
    5'h1c    : data<=16'hf00f;
    5'h1d    : data<=16'hf00c;
    5'h1e    : data<=16'hf009;
    5'h1f    : data<=16'hf006;
    
    default:data<=16'hffff;
endcase
     
end
endMODULE
2樓： >>參與討論
yadog
re
怎么輸入


輸出在那兒都沒說？

人家看不懂啊

什么叫沒輸出撒？
3樓： >>參與討論
lfk_888
選cpld器件EPM7128時，在quartus上仿真沒有輸出波形
1。選FPGA器件時在quartus上仿真輸出波形正常。
2。選cpld器件EPM7128時，在quartus上仿真沒有輸出波形，下載到EPM7128試驗板也沒有輸出。將OUTPUT [15:0] data;改為OUTPUT [7:0] data其它也修改后仿真和試驗板輸出都正常。不知什么原因�。�？

always@(posedge clk)
begin
      case (addr)
  5'h00    : data<=8'hf0;
    5'h01    : data<=8'hf6;
    5'h02    : data<=8'hf9;
    5'h03    : data<=8'hfc;
    5'h04    : data<=8'hff;
    5'h05    : data<=8'hcf;
    5'h06    : data<=8'h9f;
    5'h07    : data<=8'h6f;
    5'h08    : data<=8'h0f;

default:data<=8'hff;
endcase
     
end
endmodule
4樓： >>參與討論
zcs_1
看一下信息窗口中提示的錯誤
 
5樓： >>參與討論
lfk_888
好像輸出被綜合掉了
在編譯時信息窗口沒有提示有錯誤，但有下列警告。好像輸出被綜合掉了，不知是什么原因？有沒有解決方法啊？請各位大蝦指教？


Warning: Reduced register "data[0]~reg0" with stuck data_in PORT to stuck VALUE GND
Warning: Reduced register "data[1]~reg0" with stuck data_in PORT to stuck VALUE GND
Warning: Reduced register "data[2]~reg0" with stuck data_in PORT to stuck VALUE GND
Warning: Reduced register "data[3]~reg0" with stuck data_in PORT to stuck VALUE GND
Warning: Reduced register "data[4]~reg0" with stuck data_in PORT to stuck VALUE GND
Warning: Reduced register "data[5]~reg0" with stuck data_in PORT to stuck VALUE GND
Warning: Reduced register "data[6]~reg0" with stuck data_in PORT to stuck VALUE GND
Warning: Reduced register "data[7]~reg0" with stuck data_in PORT to stuck VALUE GND
Warning: Reduced register "data[8]~reg0" with stuck data_in PORT to stuck VALUE GND
Warning: Reduced register "data[9]~reg0" with stuck data_in PORT to stuck VALUE GND
Warning: Reduced register "data[10]~reg0" with stuck data_in PORT to stuck VALUE GND
Warning: Reduced register "data[11]~reg0" with stuck data_in PORT to stuck VALUE GND
Warning: Reduced register "data[12]~reg0" with stuck data_in PORT to stuck VALUE GND
Warning: Reduced register "data[13]~reg0" with stuck data_in PORT to stuck VALUE GND
Warning: Reduced register "data[14]~reg0" with stuck data_in PORT to stuck VALUE GND
Warning: Reduced register "data[15]~reg0" with stuck data_in PORT to stuck VALUE GND
Warning: OUTPUT pins are stuck at VCC or GND
    Warning: Pin "data[0]" stuck at GND
    Warning: Pin "data[1]" stuck at GND
    Warning: Pin "data[2]" stuck at GND
    Warning: Pin "data[3]" stuck at GND
    Warning: Pin "data[4]" stuck at GND
    Warning: Pin "data[5]" stuck at GND
    Warning: Pin "data[6]" stuck at GND
    Warning: Pin "data[7]" stuck at GND
    Warning: Pin "data[8]" stuck at GND
    Warning: Pin "data[9]" stuck at GND
    Warning: Pin "data[10]" stuck at GND
    Warning: Pin "data[11]" stuck at GND
    Warning: Pin "data[12]" stuck at GND
    Warning: Pin "data[13]" stuck at GND
    Warning: Pin "data[14]" stuck at GND
    Warning: Pin "data[15]" stuck at GND
6樓： >>參與討論
zcs_1
看一下引腳配置，是不是有的腳配到地上了
 
7樓： >>參與討論
lfk_888
我徹底暈了
1。下面這段程序選cpld器件EPM7128時，在quartus上仿真沒有輸出波形
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sin_rom is
PORT(
    clk:in std_logic;
    addr:in std_logic_vector(4 downto 0);
    dataout :out std_logic_vector(15 downto 0)
    );
end sin_rom;

architecture behav of sin_rom is
signal dataout_1:std_logic_vector(15 downto 0);
begin

PROCESS (CLK)
begin
        if CLK 'EVENT AND CLK = '1' then
    
case addr is
when "00000"=>dataout_1<="1111000000000000";--"0"
when "00001"=>dataout_1<="1111011000000001";--"1"
when "00010"=>dataout_1<="1111100100000000";--"2"
when "00011"=>dataout_1<="1111110000000000";--"3"
when "00100"=>dataout_1<="1111111100000000";--"4"
when "00101"=>dataout_1<="1100111100000000";--"5"
when "00110"=>dataout_1<="1001111100000000";--"6"
when "00111"=>dataout_1<="0110111100000000";--"7"
when "01000"=>dataout_1<="0000111100000000";--"8"
when "01001"=>dataout_1<="0000111101100000";--"9"
when "01010"=>dataout_1<="0000111110010000";--"A"
when "01011"=>dataout_1<="0000111111000000";--"B"
when "01100"=>dataout_1<="0000111111110000";--"C"
when "01101"=>dataout_1<="0000110011110000";--"D"
when "01110"=>dataout_1<="0000100111110000";--"E"
when "01111"=>dataout_1<="0000011011110000";--"F"

when "10000"=>dataout_1<="0000000011110000";--"0"
when "10001"=>dataout_1<="0000000011110110";--"1"
when "10010"=>dataout_1<="0000000011111001";--"2"
when "10011"=>dataout_1<="0000000011111100";--"3"
when "10100"=>dataout_1<="0000000011111111";--"4"
when "10101"=>dataout_1<="0000000011001111";--"5"
when "10110"=>dataout_1<="0000000010011111";--"6"
when "10111"=>dataout_1<="0000000001101111";--"7"
when "11000"=>dataout_1<="0000000000001111";--"8"
when "11001"=>dataout_1<="0110000000001111";--"9"
when "11010"=>dataout_1<="1001000000001111";--"A"
when "11011"=>dataout_1<="1100000000001111";--"B"
when "11100"=>dataout_1<="1111000000001111";--"C"
when "11101"=>dataout_1<="1111000000001100";--"D"
when "11110"=>dataout_1<="1111000000001001";--"E"
when "11111"=>dataout_1<="1111000000000110";--"F"

when others=>dataout_1<="1111111111111111";
end case;
end if;
dataout<=dataout_1;

end PROCESS;
end behav;


2。下面這段程序選cpld器件EPM7128時，在quartus上仿真輸出波形正常。library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sin_rom is
PORT(
    clk:in std_logic;
    addr:in std_logic_vector(4 downto 0);
    dataout :out std_logic_vector(15 downto 0)
    );
end sin_rom;

architecture behav of sin_rom is
signal dataout_1:std_logic_vector(15 downto 0);
begin

PROCESS (CLK)
begin
        if CLK 'EVENT AND CLK = '1' then
    
case addr is
when "00000"=>dataout_1<="1111000000000000";--"0"
when "00001"=>dataout_1<="1111011000000001";--"1"
when "00010"=>dataout_1<="1111100100000000";--"2"
when "00011"=>dataout_1<="1111110000000000";--"3"
when "00100"=>dataout_1<="1111111100000000";--"4"
when "00101"=>dataout_1<="1100111100000000";--"5"
when "00110"=>dataout_1<="1001111100000000";--"6"
when "00111"=>dataout_1<="0110111100000000";--"7"
when "01000"=>dataout_1<="0000111100000000";--"8"
when "01001"=>dataout_1<="0000111101100000";--"9"
when "01010"=>dataout_1<="0000111110010000";--"A"
when "01011"=>dataout_1<="0000111111000000";--"B"
when "01100"=>dataout_1<="0000111111110000";--"C"
when "01101"=>dataout_1<="0000110011110000";--"D"
when "01110"=>dataout_1<="0000100111110000";--"E"
when "01111"=>dataout_1<="0000011011110000";--"F"

when "10000"=>dataout_1<="0000000011110000";--"0"
when "10001"=>dataout_1<="0000000011110110";--"1"
when "10010"=>dataout_1<="1111111111111111";--"2"
when "10011"=>dataout_1<="1111111111111111";--"3"
when "10100"=>dataout_1<="1111111111111111";--"4"
when "10101"=>dataout_1<="1111111111111111";--"5"
when "10110"=>dataout_1<="1111111111111111";--"6"
when "10111"=>dataout_1<="1111111111111111";--"7"
when "11000"=>dataout_1<="1111111111111111";--"8"
when "11001"=>dataout_1<="1111111111111111";--"9"
when "11010"=>dataout_1<="1111111111111111";--"A"
when "11011"=>dataout_1<="1111111111111111";--"B"
when "11100"=>dataout_1<="1111111111111111";--"C"
when "11101"=>dataout_1<="1111111111111111";--"D"
when "11110"=>dataout_1<="1111111111111111";--"E"
when "11111"=>dataout_1<="1111111111111111";--"F"

when others=>dataout_1<="1111111111111111";
end case;
end if;
dataout<=dataout_1;

end PROCESS;
end behav;

實在沒辦法了，請各位大蝦幫幫忙，
8樓： >>參與討論
lfk_888
已解決了
對不起大家。已解決了，我用quartus5.0有問題，升級到5.1就OK了。我也不知為什么
9樓： >>參與討論
quantins
暈
～～
10樓： >>參與討論
jadengil
這問題也太大了吧
 
參與討論
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