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latch-up是怎麼一回事情? |
| 作者：epprom 欄目：集成電路 |
請教一下專業(yè)人士集成電路中的latch-up現(xiàn)象是怎麼一回事情? 還有實際的可靠性測試中l(wèi)atch-up測試是怎樣測試的,具體的標準是什麼? |
| 2樓： | >>參與討論 |
| 作者： callcfg 于 2005/12/3 13:13:00 發(fā)布：
書上有的 有專門的一本書，叫：CMOS技術(shù)的閂鎖效應問題及其解決方法。 |
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| 3樓： | >>參與討論 |
| 作者： iclover 于 2005/12/9 14:42:00 發(fā)布：
相關(guān)資料我有 需要可聯(lián)系我，QQ66704813 |
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| 4樓： | >>參與討論 |
| 作者： code631 于 2005/12/21 1:49:00 發(fā)布：
參考一下 A latchup is the inadvertent creation of a low-impedance path between the POWER supply rails as a result of triggering a parasitic DEVICE, which then opens and acts as a SHORT CIRCUIT, leading to ceasement of proper function of the PART and perhaps even its destruction with the overcurrent. Soft reset won't improve the situation, a POWER cycle is required. The parasitic structure is usually an equivalent of a thyristor (also called SCR), the P-N-P-N structure acting as a PNP and a NPN TRANSISTOR, stacked on each other. When either one of them conducts, the other one conducts too, and they both KEEP each other in saturation for as LONG as the structure is forward-biased and some current flows through it - which usually means until a POWER-down. The SCR parasitic structure is formed as a PART of the totem-pole PMOS and NMOS TRANSISTOR pair on the OUTPUT drivers of the gates. The latchup does not have to happen ONLY between the POWER rails; it can happen anywhere where the required parasitic structure exists. A spike of positive or negative voltage on an input or OUTPUT pin of a DIGITAL chip, exceeding the rail voltage by more than a DIODE drop, is a common cause of a latchup. Another cause is supply voltage exceeding the absolute maximum rating, leading to a breakdown of some internal junction - a common source are transient spikes in POWER supply. A common problem with CIRCUITs with multiple supply voltages that do not come up in the proper order after a POWER-up, leading to voltages on data lines exceeding the input rating of PARTs that do not get their supply voltage yet. Yet another common cause of latchups is ionizing radiation. It is possible to design chips that are latchup-resistant, where layer of insulating oxide (called a trench) surrounds both the NMOS and the PMOS TRANSISTORs. This breaks the parasitic SCR structure between these TRANSISTORs. Such PARTs are important in the cases where the proper sequencing of POWER and signals can not be guaranteed, eg. in hot swap DEVICEs. Most SOI DEVICEs are inherently latchup-resistant. Another possibility for a latchup prevention is the Latchup Protection TECHNOLOGY CIRCUIT. When a latchup is detected, the LPC CIRCUIT shuts down the chip and holds it POWERed-down for a preset time. |
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