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請(qǐng)教一個(gè)quartus編譯時(shí)的警告

作者：雷風(fēng)　欄目：EDA技術(shù)

請(qǐng)教一個(gè)quartus編譯時(shí)的警告
1 variable "clock_divide" may not be assigned a new VALUE in every possible path through the Always Construct. Variable "clock_divide" holds its previous VALUE in every path with no new VALUE assignment, which may create a combinational loop in the current design.

這個(gè)警告的意思是不是說我必須在always每一條可能的路徑中都給state_next一個(gè)明確的值？

2 Latch counter[4] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal state.process

這個(gè)警告什么意思我就一點(diǎn)也不明白了
還請(qǐng)大家指點(diǎn)

2樓：

>>參與討論

作者：雷風(fēng) 于 2005/7/9 21:34:00 發(fā)布：

沒有高手愿意幫忙么
頂
沒有高手愿意幫忙么？
程序如下：
`define freq_div 32      //分頻系數(shù)
MODULE pwm
(
clk,
pwm_enable,
resetn,
pwm_out,
key_add,
key_dec,
key_duty,
key_clock
);
//Inputs
input clk;     //Input Clock to be divided
input pwm_enable;   //Enable signal,撥碼開關(guān)1,pin58
input resetn;    //Reset,pin23
input key_add;    //pin 48
input key_dec;    //pin 49
input key_duty;    //pin 57，you must press this key first
input key_clock;   //pin 62
//Outputs
OUTPUT pwm_out;       //PWM OUTPUT,pin 187
//Signal Declarations
reg [31:0] counter;   //PWM Internal Counter
reg pwm_out;    //PWM OUTPUT
reg [31:0] duty_cycle;  //Duty Cycle VALUE
reg [31:0] clock_divide; //Clock Divide VALUE
reg [2:0] state;
reg [2:0] state_next;
reg key_done;      //按鍵掃描完成
reg key_in_reg;    //有鍵按下，進(jìn)入按鍵處理程序

//parameter declarations
parameter  idle =   3'B001,
    key_in =  3'B010,
    PROCESS =  3'B100;

always @( posedge clk or negedge resetn )
begin
  if( !resetn )
   begin
    state = `freq_div )
      begin
       key_done = 1'b1;
       state_next = PROCESS;
      end
     else
      begin
       key_done = 1'b0;
       state_next = key_in;
      end
    end

   PROCESS:
    begin
     if( pwm_enable )
      begin
       if ( counter >= duty_cycle )
        begin
         pwm_out = 1'b1;
         if (counter >= clock_divide)
          counter = 0;
        end
       else
        begin
         if (counter == 0)
          pwm_out = 1'b0;
         else
          pwm_out = pwm_out;
         counter = counter + 1;
        end
      end
     else
      begin
      counter = counter;
      pwm_out = 1'b0;
      if( key_in_reg )
       state_next = key_in;
      else state_next = PROCESS;
      end
    end
   default:
    state_next = idle;
  endcase
end
always @( negedge key_add or negedge key_dec or negedge key_duty or negedge key_clock )
begin
  if( !key_add )
  begin
   duty_cycle = duty_cycle + 1;
   if( duty_cycle > clock_divide )
    duty_cycle = duty_cycle;
   key_in_reg <= 1;
  end
  if( !key_dec )
  begin
   duty_cycle = duty_cycle - 1;
   if( duty_cycle == 32'd0 )
    duty_cycle = 0;
   key_in_reg <= 1;
  end
  if( !key_duty )
   begin
    duty_cycle = duty_cycle + 1;
    key_in_reg <= 1;
   end
  if( !key_clock )
   begin
    clock_divide = clock_divide + 1;
    key_in_reg <= 1;
   end
end

endMODULE

3樓：	>>參與討論
作者： oo1xx 于 2005/7/11 17:28:00 發(fā)布：有l(wèi)atch！一個(gè)是狀態(tài)不完全，一個(gè)是有l(wèi)atch

參與討論

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