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自己定義的IP核怎么用？？？？ |
| 作者：aliao2003 欄目：EDA技術(shù) |
請問我自己定義的IP核怎么不可以用，該怎么用？ 我想在XC2S50內(nèi)部自己定義一個16*640的內(nèi)部RAM ，我用IP CORE GEN 在向?qū)Ｊ较律闪艘粋�IP核，可是我在同一項目目錄下的TOP文件中使用該IP核的時候，綜合老是報錯，說是找不到IP的MODULE 。請問是怎么回事呢？ 生成IP 核后我還要做些什么工作，保證我的IP核可以用，怎么弄呢？ 謝謝�。。�！ |
| 2樓： | >>參與討論 |
| 作者： aliao2003 于 2005/4/14 10:27:00 發(fā)布：
單獨編譯報錯 自己頂一下！ IP生成的.V文件單獨編譯的時候通不過是什么原因呢？ |
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| 3樓： | >>參與討論 |
| 作者： aliao2003 于 2005/4/14 10:30:00 發(fā)布：
編譯過程 Started PROCESS "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= WARNING:Xst:878 - myLINE.v LINE 102: Unrecognized directive. Ignoring. Compiling source file "myLINE.v" MODULE <myLINE> compiled No errors in compilation Analysis of file <myLINE.prj> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top MODULE <myLINE>. WARNING:Xst:37 - UNKNOWN property "fpga_dont_touch". ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit <myLINE>. Related source file is myLINE.v. Unit <myLINE> synthesized. ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * ADVANCED HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit <myLINE> ... Loading DEVICE for application Xst from file 'v50.nph' in environment C:/XILINX. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block myLINE, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= DEVICE utilization summary: --------------------------- Selected DEVICE : 2s50pq208-6 ========================================================================= TIMING REPORT Clock Information: ------------------ No clock signals found in this design Timing Summary: --------------- Speed Grade: -6 MINIMUM period: No path found MINIMUM input arrival time before clock: No path found Maximum OUTPUT required time after clock: No path found Maximum combinational path delay: No path found ========================================================================= Completed PROCESS "Synthesize". Started PROCESS "Translate". Command LINE: ngdbuild -intstyle ise -dd d:\TEST\ipTEST\myram/_ngo -i -p xc2s50-pq208-6 myLINE.ngc myLINE.ngd Reading NGO file "D:/TEST/ipTEST/myram/myLINE.ngc" ... Reading component libraries for design expansion... Loading design MODULE "D:\TEST\ipTEST\myram/myLINE.ngc"... WARNING:NgdBuild:578 - Design contains no instances. Checking timing specifications ... Checking expanded design ... ERROR:NgdBuild:605 - logical root block 'myLINE' with type 'myLINE' is unexpanded. Symbol 'myLINE' is not supported in target 'spartan2'. NGDBUILD Design Results Summary: NUMBER of errors: 1 NUMBER of warnings: 0 Total MEMORY usage is 37404 kilobytes One or more errors were found during NGDBUILD. No NGD file will be written. Writing NGDBUILD log file "myLINE.bld"... ERROR: NGDBUILD failed PROCESS "Translate" did not complete. 幫忙看看，是什么原因呢？ |
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| 4樓： | >>參與討論 |
| 作者： aliao2003 于 2005/4/14 10:38:00 發(fā)布：
自己分析 IP是用工具生成的，不會是語法或別的什么不可綜合的問題，應該是軟件在某些地方?jīng)]有設置好！請高手指點！問題捆饒我很久了�。�！ 謝謝了�。�！ |
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