音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

ISPXPGA1200E Datasheet

  • ISPXPGA1200E

  • ispXPGA Family

  • 115頁

  • LATTICE   LATTICE

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

July 2008
Includes
High-
,
Performance
Low-Cost
鈥淓-Series鈥?/div>
ispXPGA Family
廬
Data Sheet DS1026
鈻?/div>
Non-volatile, In鏗乶itely Recon鏗乬urable
鈥?Instant-on - Powers up in microseconds via
on-chip E
2
CMOS
廬
based memory
鈥?No external con鏗乬uration memory
鈥?Excellent design security, no bit stream to intercept
鈥?Recon鏗乬ure SRAM based logic in milliseconds
鈥?Microprocessor con鏗乬uration interface
鈥?Program E
2
CMOS while operating from SRAM
鈻?/div>
Eight sysCLOCK鈩?Phase Locked Loops
(PLLs) for Clock Management
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
True PLL technology
10MHz to 320MHz operation
Clock multiplication and division
Phase adjustment
Shift clocks in 250ps steps
鈻?/div>
High Logic Density for System-level
Integration
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
139K to 1.25M system gates
160 to 496 I/O
1.8V, 2.5V, and 3.3V V
CC
operation
Up to 414Kb sysMEM鈩?embedded memory
鈻?/div>
sysIO鈩?for High System Performance
鈥?High speed memory support through SSTL and
HSTL
鈥?Advanced buses supported through PCI, GTL+,
LVDS, BLVDS, and LVPECL
鈥?Standard logic supported through LVTTL,
LVCMOS 3.3, 2.5 and 1.8
鈥?5V tolerant I/O for LVCMOS 3.3 and LVTTL
interfaces
鈥?Programmable drive strength for series termination
鈥?Programmable bus maintenance
鈻?/div>
High Performance Programmable Function
Unit (PFU)
鈥?Four LUT-4 per PFU supports wide and narrow
functions
鈥?Dual 鏗俰p-鏗俹ps per LUT-4 for extensive pipelining
鈥?Dedicated logic for adders, multipliers, multiplex-
ers, and counters
鈻?/div>
Flexible Memory Resources
鈥?Multiple sysMEM Embedded RAM Blocks
鈥?Single port, Dual port, and FIFO operation
鈥?64-bit distributed memory in each PFU
鈥?Single port, Double port, FIFO, and Shift
Register operation
鈻?/div>
Two Options Available
鈥?High-performance sysHSI (standard part number)
鈥?Low-cost, no sysHSI (鈥淓-Series鈥?
鈻?/div>
Flexible Programming, Recon鏗乬uration,
and Testing
鈥?Supports IEEE 1532 and 1149.1
Table 1. ispXPGA Family Selection Guide
ispXPGA 125/E
System Gates
PFUs
LUT-4s
Logic FFs
sysMEM Memory
Distributed Memory
EBR
sysHSI Channels
1
User I/O
Packaging
139K
484
1936
3.8K
92K
30K
20
4
160/176
256 fpBGA
516 fpBGA
2
鈻?/div>
sysHSI鈩?Capability for Ultra Fast Serial
Communications
鈥?Up to 800Mbps performance
鈥?Up to 20 channels per device
鈥?Built in Clock Data Recovery (CDR) and
Serialization and De-serialization (SERDES)
ispXPGA 200/E
210K
676
2704
5.4K
111K
43K
24
8
160/208
256 fpBGA
516 fpBGA
2
ispXPGA 500/E
476K
1764
7056
14.1K
184K
112K
40
12
336
516 fpBGA
2
900 fpBGA
ispXPGA 1200/E
1.25M
3844
15376
30.7K
414K
246K
90
20
496
680 fpSBGA
2
900 fpBGA
1. 鈥淓-Series鈥?does not support sysHSI.
2. FH516 package was converted to F516 via PCN# 09A-08.
漏 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speci鏗乧ations and information herein are subject to change without notice.
www.latticesemi.com
1
DS1026_14.1

ISPXPGA1200E相關(guān)型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！