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ISPPAC81-01SI Datasheet

  • ISPPAC81-01SI

  • In-System Programmable Analog Circuit

  • 20頁

  • LATTICE   LATTICE

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ispPAC81
In-System Programmable Analog Circuit
October 2001
Data Sheet
Features
鈻?/div>
In-System Programmable(ISP鈩? Analog
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Instrument Ampli鏗乪r Gain Stage
Precision Active Filtering (10kHz to 75kHz)
Continuous-Time Fifth Order Low Pass Topology
Dual, A/B Con鏗乬uration Memory
Non-Volatile E
2
CMOS
廬
Cells
IEEE 1149.1 JTAG Serial Port Programming
Functional Block Diagram
TMS
TCK
TDI
TDO
CS
CAL
ENSPI
GND
1
2
IA
OA
16 VS
15 TEST
14 OUT+
5th Order LPF
E2CMOS Cfg A
Ref & Auto-Cal
E2CMOS Cfg B
ISP Control
3
4
5
6
7
8
13 OUT鈥?/div>
12 TEST
11 IN+
10 IN鈥?/div>
9 VREFOUT
鈻?/div>
Unique Flexibility and Performance
鈥?Programmable Gain Range (0dB to 20dB)
鈥?Implements Multiple Filter Types: Elliptical,
Chebyshev, Butterworth
鈥?Low Distortion (THD < -80dB at 10kHz)
鈥?Auto-Calibrated Input Offset Voltage
鈻?/div>
True Differential I/O
鈥?High CMR Instrument Ampli鏗乪r Input
鈥?2.5V Common Mode Reference on Chip
鈥?Rail-to-Rail Voltage Outputs
ispPAC81
Description
The ispPAC81 is a member of the Lattice family of In-System
Programmable analog circuits, digitally con鏗乬ured via nonvol-
atile E
2
CMOS technology.
Analog building blocks, called PACell鈩?s), replace traditional
analog components such as opamps, eliminating the need for
external resistors and capacitors. With no requirement for
external con鏗乬uration components, ispPAC81 expedites the
design process, simplifying prototype circuit implementation
and change, while providing high-performance integrated
functionality. With all components on chip, there is no longer a
concern of performance degradation due to component mis-
match or other external factors. The ispPAC81 provides reli-
able and repeatable performance, every time.
Designers con鏗乬ure the ispPAC81 and verify its performance
using PAC-Designer
廬
, an easy-to-use, Microsoft Windows
廬
compatible program. A 鏗乴ter con鏗乬uration database is pro-
vided whereby thousands of different con鏗乬urations can be
realized. No special understanding of 鏗乴ter synthesis is
required beyond that of general speci鏗乧ations such as corner
frequency and stopband attenuation, etc. The software lists
the possible choices that meet the designer鈥檚 speci鏗乧ations
which can then be loaded directly into either of two device (A/
B) con鏗乬urations from the lookup table. Device programming
is supported using PC parallel port I/O operations.
The ispPAC81 is con鏗乬ured through its IEEE Standard 1149.1
compliant serial port. The 鏗俥xible In-System Programming
capability enables programming, veri鏗乧ation and recon鏗乬ura-
tion, if desired, directly on the printed circuit board.
鈻?/div>
Single Supply 5V Operation
鈥?Power Dissipation of 133mW
鈥?16-Pin Plastic SOIC, PDIP Packages
鈻?/div>
Applications Include Integrated
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Single +5V Supply Signal Conditioning
Programmable Filters With Fully Differential I/O
Analog Front Ends, 12-Bit Data Acq. Systems
DSP System Front End Signal Conditioning
High-Performance Reconstruction Filters
Typical Application Diagram
5V
ispPAC81
5V
12-Bit Differential
Input ADC
Ain+
Ain-
A/B & Gain
SPI Control
VREFout
Reference
Vin
5V
DSP
www.latticesemi.com
1
pac81_01

ISPPAC81-01SI 產(chǎn)品屬性

  • Lattice

  • SPLD - 簡單可編程邏輯器件

  • ISPPA

  • 9 ns

  • 3 V to 3.6 V

  • 85 C

  • - 40 C

  • SOIC-16

  • SMD/SMT

  • 40

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