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ISPLSI1048EA-100LQ128 Datasheet

  • ISPLSI1048EA-100LQ128

  • In-System Programmable High Density PLD

  • 14頁(yè)

  • LATTICE   LATTICE

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ispLSI 1048EA
廬
In-System Programmable High Density PLD
Features
鈥?HIGH DENSITY PROGRAMMABLE LOGIC
鈥?8,000 PLD Gates
鈥?96 I/O Pins, Eight Dedicated Inputs
鈥?288 Registers
鈥?High-Speed Global Interconnects
鈥?Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
鈥?Small Logic Block Size for Random Logic
鈥?Functionally Compatible with ispLSI 1048C and 1048E
鈥?NEW FEATURES
鈥?100% IEEE 1149.1 Boundary Scan Testable
鈥?ispJTAG鈩?In-System Programmable Via IEEE 1149.1
(JTAG) Test Access Port
鈥?User Selectable 3.3V or 5V I/O supports Mixed
Voltage Systems (V
CCIO
Pin)
鈥?Open Drain Output Option
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?/div>
f
max
= 170 MHz Maximum Operating Frequency
鈥?/div>
t
pd
= 5.0 ns Propagation Delay
鈥?TTL Compatible Inputs and Outputs
鈥?Electrically Eraseable and Reprogrammable
鈥?Non-Volatile
鈥?100% Tested at Time of Manufacture
鈥?IN-SYSTEM PROGRAMMABLE
鈥?Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
鈥?Reprogram Soldered Devices for Faster Prototyping
鈥?OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
鈥?Complete Programmable Device Can Combine Glue
Logic and Structured Designs
鈥?Enhanced Pin Locking Capability
鈥?Four Dedicated Clock Input Pins
鈥?Synchronous and Asynchronous Clocks
鈥?Programmable Output Slew Rate Control to
Minimize Switching Noise
鈥?Flexible Pin Placement
鈥?Optimized Global Routing Pool Provides Global
Interconnectivity
鈥?ispDesignEXPERT鈩?鈥?LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
鈥?Superior Quality of Results
鈥?Tightly Integrated with Leading CAE Vendor Tools
鈥?Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER鈩?/div>
鈥?PC and UNIX Platforms
Functional Block Diagram
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
A0
Output Routing Pool
Output Routing Pool
E7 E6 E5 E4 E3 E2 E1 E0
D7
D5
Output Routing Pool
D Q
A1
A2
A3
A4
A5
A6
A7
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
D6
Logic
D Q
Global Routing Pool (GRP)
Array
D Q
GLB
D4
D3
D2
D1
D0
D Q
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool
CLK
0139A/1048EA
Description
The ispLSI 1048EA is a High Density Programmable
Logic Device containing 288 Registers, 96 Universal I/O
pins, eight Dedicated Input pins, four Dedicated Clock
Input pins, two dedicated Global OE input pins, and a
Global Routing Pool (GRP). The GRP provides complete
interconnectivity between all of these elements. The
ispLSI 1048EA features 5V in-system programmability
and in-system diagnostic capabilities via IEEE 1149.1
Test Access Port. The ispLSI 1048EA offers non-volatile
reprogrammability of the logic, as well as the intercon-
nect to provide truly reconfigurable systems. A functional
superset of the ispLSI 1048 architecture, the ispLSI
1048EA device adds user selectable 3.3V or 5V I/O and
open-drain output options.
The basic unit of logic on the ispLSI 1048EA device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1鈥7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 1048EA device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinato-
rial or registered. Inputs to the GLB come from the GRP
and dedicated inputs. All of the GLB outputs are brought
back into the GRP so that they can be connected to the
inputs of any other GLB on the device.
Copyright 漏 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
June 2000
1048ea_03
1

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