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ZR36015 Datasheet

  • ZR36015

  • RASTER TO BLOCK CONVERTER

  • 27頁

  • ETC

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ZR36015
PRELIMINARY
RASTER TO BLOCK CONVERTER
FEATURES
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Real Time Raster to/from Block Conversion
1/2 Decimation Processing in the Horizontal Direction
30 MHz Maximum Clock Rate
Only Image in Preset Window is Converted
Compatable with Zorans ZR36050 JPEG Coder and
ZR36011 Color Space Converter
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Supports 1:0:0,4:2:2,and 4:1:1 data formats
100-pin plastic quad 鏗俛t package (PQFP)
TTL level Input/Output
Synchronous data and controls
Low power consumption: 0.45W (Typ.)
CMOS circuit operating with a single 5V power supply
APPLICATIONS
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Image processing
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Multi-media
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Scanners
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Image Storage
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Image Capture
DESCRIPTION
The ZR36015 performes raster to/from block conversion for
image compression and expansion applications, and it can be
connected directly to the ZR36050 JPEG coder and the
ZR36011 Color Space Converter.
An image compression system can be easily constructed using
the ZR36015 with the ZR35060 and ZR36011.
The ZR36015 uses a double buffered external SRAM Strip
Buffer to support raster to/from block conversion and block inter-
leave.
The maximum number of pixels that can be processed per line
is 8K. The maximum number of lines that can be prcessed per
image is 16K. These numbers vary according to the mode of
operation.
The ZR36015 supports 4:0:0, 4:1:1, and 4:2:2 data formats, and
one half decimation in horizontal direction during compression.
The maximum data transfer rate to the ZR36050 coder is 30
MHz.
[The ZR36015 is fabricated with an advanced low-power CMOS
technology, making it suitable for use in low-power, cost sensi-
tive applications. The device is availiable in a 100 pin , Plastic
Quad Flat Package (PQFP).]
Host Interface
SPH
WR
RD
ADD(1:0)
Internal Register Control
CBSY
Raster/Block
Address
Generator
MWE
MOE
MADD(15:0)
Memory
Interface
8
PXDATA(15:0)
CBUSY
HEN
VEN
WINDOW
BSY
CLKCSC
SPH
RD
WR
ADD(1:0)
SYSCLK
RESET
MWE
MOE
16
PXDATA(15:0)
1/2
Decimation
I/F
Selector
MDATA(15:0)
Pixel
Interface
MADD(15:0)
16
Memory
Interface
Sub
Buffer
I/F
Pixel
Interface
HEN
VEN
WINDOW
BSY
CLKCSC
Window
Control
MDATA(15:0)
RESET
SYSCLK
Host
Interface
2
8
BDATA(7:0)
COE
EOS
STOP
DSYNC
Coder
Interface
Interface Logic
I/F
System
Clock
DSYNC
EOS
STOP
COE
Coder Interface
BDATA(7:0)
System
Reset
Figure 1. ZR36015 Block Diagram
ZORAN Corporation
Figure 2. ZR36015 Logical Pinout
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FAX (408) 986-1240
June 1993
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1705 Wyatt Drive
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Santa Clara, CA 95054
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(408) 986-1314
This document was created with FrameMaker 4.0.4

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