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ZL50407 Datasheet

  • ZL50407

  • Lightly Managed/Unmanaged 8-Port 10/100M + 1-Port 10/100/100...

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ZL50407
Lightly Managed/Unmanaged
8-Port 10/100M +
1-Port 10/100/1000M Ethernet Switch
Data Sheet
Features
鈥?/div>
Integrated Single-Chip 10/100/1000 Ethernet
Switch
鈥?Eight 10/100 Mbps auto-negotiating Fast
Ethernet (FE) ports with RMII, MII, GPSI,
Reverse MII & Reverse GPSI interface options
鈥?One 10/100/1000 Mbps auto-negotiating port
with GMII & MII interface options, that can be
used as a WAN uplink or as a 9th port
Operates stand-alone or can be cascaded with a
second ZL50407 to reach 16 ports
Embedded 2 Mbits (256 KBytes) internal memory
鈥?supports up to 4 K byte frames
L2 switching
鈥?MAC address self learning, up to 4 K MAC
addresses using internal table
鈥?Supports the following spanning standards
- IEEE 802.1D spanning tree
- IEEE 802.1w rapid spanning tree
鈥?Supports Ethernet multicasting and
broadcasting and flooding control
VLAN Support
鈥?Supports port-based VLAN
Ordering Information
ZL50407GDC
208 Pin LBG螒
August 2004
-40擄C to +85擄C
鈥?/div>
CPU access supports the following interface
options:
鈥?Serial interface in lightly managed mode, or in
unmanaged mode with optional I
2
C EEPROM
interface
Failover Features
鈥?Rapid link failure detection using
hardware-generated heartbeat packets
鈥?link failover in less than 50 ms
Rate Control (both ingress and egress)
鈥?Bandwidth rationing, Bandwidth on demand,
SLA (Service Level Agreement)
鈥?Smooth out traffic to uplink port
鈥?Ingress Rate Control
- Back pressure
- Flow Control
- WRED (Weighted Random Early Discard)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
C
P
U
Serial
ZL50407
GMII / MII
8-Port 10/100M + 1G
Ethernet Switch
EEPROM
I
2
C
10/100/
1000
PHY
RMII / MII / GPSI
Quad
10/100
PHY
Quad
10/100
PHY
Figure 1 - System Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.

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