ZL50405GDC Datasheet

IC型號(hào)：
ZL50405GDC
PDF描述：
Managed5-Port 10/100 M Ethernet Switch
文件大?。?/label>
762.44KB
PDF頁(yè)數(shù)：
132頁(yè)
芯片廠家：
ZARLINK

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ZL50405

Managed5-Port 10/100 M Ethernet Switch

Data Sheet

Features

鈥?/div>

Integrated Single-Chip 10/100 Ethernet Switch

鈥?Four 10/100 Mbps auto-negotiating Fast

Ethernet (FE) ports with RMII, MII, GPSI,

Reverse MII & Reverse GPSI interface options

鈥?One 10/100 Mbps auto-negotiating port with

MII interface option, that can be used as a

WAN uplink or as a 9th port

鈥?a 10/100 Mbps Fast Ethernet (FE) CPU port

with Reverse MII interface option

Embedded 2 Mbits (256 KBytes) internal memory

鈥?supports up to 4 K byte frames

L2 switching

鈥?MAC address self learning, up to 4 K MAC

addresses using internal table

鈥?Supports IP Multicast with IGMP snooping, up

to 4 K IP Multicast groups

鈥?Supports the following spanning standards

- IEEE 802.1D spanning tree

- IEEE 802.1w rapid spanning tree

鈥?Supports Ethernet multicasting and

broadcasting and flooding control

VLAN Support

鈥?Supports port-based VLAN and tagged-based

Ordering Information

ZL50405GDC

208 Pin LBGA

January 2005

-40擄C to +85擄C

VLAN (IEEE 802.1Q), up to 4 K VLANs

鈥?Supports both shared VLAN learning (SVL)

and independent VLAN learning (IVL)

CPU access supports the following interface

options:

鈥?8/16-bit parallel and Serial+MII interface in

managed mode

鈥?Serial interface in lightly managed mode, or in

unmanaged mode with optional I

C EEPROM

interface

Failover Features

鈥?Rapid link failure detection using

hardware-generated heartbeat packets

鈥?link failover in less than 50 ms

Rate Control (both ingress and egress)

鈥?Bandwidth rationing, Bandwidth on demand,

鈥?/div>

8/16-bit

Serial

ZL50405

MII

5-Port 10/100M

Ethernet Switch

EEPROM

10/100

PHY

RMII / MII / GPSI

Quad

10/100

PHY

Figure 1 - System Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

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