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ZL50400GDC Datasheet

  • ZL50400GDC

  • Lightly Managed/Unmanaged 9-Port 10/100 M Ethernet Switch

  • 124頁

  • ZARLINK   ZARLINK

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ZL50400
Lightly Managed/Unmanaged
9-Port 10/100 M Ethernet Switch
Data Sheet
Features
鈥?/div>
Integrated Single-Chip 10/100 Ethernet Switch
鈥?Eight 10/100 Mbps auto-negotiating Fast
Ethernet (FE) ports with RMII, MII, GPSI,
Reverse MII & Reverse GPSI interface options
鈥?One 10/100 Mbps auto-negotiating port with
MII interface option, that can be used as a
WAN uplink or as a 9th port
Embedded 2 Mbits (256 KBytes) internal memory
鈥?supports up to 4 K byte frames
L2 switching
鈥?MAC address self learning, up to 4 K MAC
addresses using internal table
鈥?Supports the following spanning standards
- IEEE 802.1D spanning tree
- IEEE 802.1w rapid spanning tree
鈥?Supports Ethernet multicasting and
broadcasting and flooding control
VLAN Support
鈥?Supports port-based VLAN
CPU access supports the following interface
options:
鈥?Serial interface in lightly managed mode, or in
unmanaged mode with optional I
2
C EEPROM
interface
Ordering Information
ZL50400GDC
208 Pin LBGA
January 2005
-40擄C to +85擄C
鈥?/div>
Failover Features
鈥?Rapid link failure detection using
hardware-generated heartbeat packets
鈥?link failover in less than 50 ms
Rate Control (both ingress and egress)
鈥?Bandwidth rationing, Bandwidth on demand,
SLA (Service Level Agreement)
鈥?Smooth out traffic to uplink port
鈥?Ingress Rate Control
- Back pressure
- Flow Control
- WRED (Weighted Random Early Discard)
鈥?Egress Rate Control
鈥?Down to 16 kbps Rate Control granularity
Per queue traffic shaper on uplink port
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
C
P
U
Serial
ZL50400
MII
9-Port 10/100M
Ethernet Switch
EEPROM
I
2
C
10/100
PHY
RMII / MII / GPSI
Quad
10/100
PHY
Quad
10/100
PHY
Figure 1 - System Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.

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