ZL50116 Datasheet

IC型號：
ZL50116
PDF描述：
32, 64 and 128 Channel CESoP Processors
文件大小：
1150.03KB
PDF頁數(shù)：
95頁
芯片廠家：
ZARLINK

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ZL50115/16/17/18/19/20

32, 64 and 128 Channel CESoP

Processors

Data Sheet

Features

General

鈥?/div>

Circuit Emulation Services over Packet (CESoP)

transport for MPLS, IP and Ethernet networks

On chip timing & synchronization recovery across

a packet network

On chip dual reference Stratum 3 DPLL

Grooming capability for Nx64 Kbps trunking

Fully compatible with Zarlink's ZL50110, ZL50111

and ZL50114 CESoP processors

鈥?/div>

ZL50115GAG

ZL50116GAG

ZL50117GAG

ZL50118GAG

ZL50119GAG

ZL50120GAG

April 2005

Ordering Information

324

Ball

PBGA

trays,

bake

dry

pack

-40擄C to +85擄C

Up to 128 bi-directional 64 Kbps channels

Direct connection to LIUs, framers, backplanes

Circuit Emulation Services

鈥?/div>

Complies with ITU-T recommendation Y.1413

Complies with IETF PWE3 draft standards

CESoPSN and SAToP

Complies with CESoP Implementation

Agreements from MEF 8 and MFA 8.0.0

Structured, synchronous CESoP with clock

recovery

Unstructured, asynchronous CESoP with integral

per-stream clock recovery

Customer Side Packet Interfaces

鈥?100 Mbps MII Fast Ethernet (ZL50118/19/20 only)

(may also be used as a second provider side packet

interface)

Provider Side Packet Interfaces

鈥?/div>

100 Mbps MII Fast Ethernet or 1000 Mbps

GMII/TBI Gigabit Ethernet

Customer Side TDM Interfaces

鈥?/div>

Up to 4 T1/E1, 1 J2, 1 T3/E3, or 1 STS-1 ports

H.110, H-MVIP, ST-BUS backplane

4 T1/E1, 1 J2/T3/E3 or 1 STS-1 ports

H.110, H-MVIP, ST-BUS backplanes

TDM

Interface

(LIU, Framer, Backplane)

Multi-Protocol

Packet

Processing

Engine

PW, RTP, UDP,

IPv4, IPv6, MPLS,

ECID, VLAN, User

Defined, Others

Dual

Packet

Interface

MAC

(MII, GMII, TBI)

Per Port DCO for

Clock Recovery

100 Mbps MII

Fast Ethernet

On Chip Packet Memory

(Jitter Buffer Compensation for 128 ms of Packet Delay Variation)

Dual Reference

Stratum 3 DPLL

Host Processor

Interface

32-bit Motorola compatible

DMA for signaling packets

Backplane

Clocks

JTAG

Figure 1 - ZL50115/16/17/18/19/20 High Level Overview

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

100 Mbps MII Fast Ethernet

1000 Mbps GMII/TBI Gigabit Ethernet

型號

版本

描述

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