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ZL50053QCC Datasheet

  • ZL50053QCC

  • 8 K Channel Digital Switch with High Jitter Tolerance, Singl...

  • 67頁(yè)

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ZL50051/3
8 K Channel Digital Switch with High Jitter
Tolerance, Single Rate (8 or 16 Mbps),
and 64 Inputs and 64 Outputs
Data Sheet
Features
鈥?/div>
8,192 channel x 8,192 channel non-blocking
unidirectional switching. The Backplane and
Local inputs and outputs can be combined to form
a non-blocking switching matrix with 64 input
streams and 64 output streams
4,096 channel x 4,096 channel non-blocking
Backplane input to Local output stream switch
4,096 channel x 4,096 channel non-blocking
Local input to Backplane output stream switch
4,096 channel x 4,096 channel non-blocking
Backplane input to Backplane output switch
4,096 channel x 4,096 channel non-blocking
Local input to Local output stream switch
Backplane port accepts 32 input and 32 output
ST-BUS streams with a fixed data rate of
8.192 Mbps, or 16 input and 16 output ST-BUS
streams with a fixed data rate of 16.384 Mbps
Local port accepts 32 input and 32 output ST-
BUS streams with a fixed data rate of
8.192 Mbps, or 16 input and 16 output ST-BUS
streams with a fixed data rate of 16.384 Mbps
Exceptional input clock jitter tolerance (17 ns)
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Ordering Information
ZL50051GAC
ZL50053QCC
256 ball PBGA
256 pin LQFP
December 2003
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-40擄C to +85擄C
Per-stream bit delay for Local and Backplane
input streams
Per-stream advancement for Local and Backplane
output streams
Constant 2-frame throughput delay for frame
integrity
Per-channel high impedance output control for
Local and Backplane streams
Per-channel driven-high output control for Local
and Backplane streams
Per-channel message mode for Local and
Backplane output streams
Connection memory block programming for fast
device initialization
鈥?/div>
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V
DD_IO
V
DD_CORE
V
SS (GND)
RESET
ODE
BSTi0-31
Backplane Data Memories
(4,096 channels)
Local
Interface
LSTi0-31
Backplane
Interface
BSTo0-31
Backplane
Connection Memory
(4,096 locations)
Local
Connection Memory
(4,096 locations)
Local
Interface
LSTo0-31
BORS
Local Data Memories
(4,096 channels)
LORS
FP8i
Input
Timing Unit
Output
Timing
Unit
FP8o
FP16o
C8o
C16o
C8i
PLL
Microprocessor Interface
and Internal Registers
Test Port
V
DD_PLL
DS CS R/W
A14-0
DTA
D15-0
TMS TDi TDo TCK TRST
Figure 1 - ZL50051/3 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.

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