ZL50015GAC Datasheet

IC型號：
ZL50015GAC
PDF描述：
Enhanced 1 K Digital Switch with Stratum 4E DPLL
文件大?。?/label>
917.89KB
PDF頁數(shù)：
122頁
芯片廠家：
ZARLINK

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ZL50015

Enhanced 1 K Digital Switch with

Stratum 4E DPLL

Data Sheet

Features

鈥?/div>

1024 channel x 1024 channel non-blocking digital

Time Division Multiplex (TDM) switch at 4.096,

8.192 and 16.384 Mbps or using a combination of

ports running at 2.048, 4.096, 8.192 and

16.384 Mbps

16 serial TDM input, 16 serial TDM output

streams

Integrated Digital Phase-Locked Loop (DPLL)

exceeds Telcordia GR-1244-CORE Stratum 4E

specifications

Output clocks have less than 1 ns of jitter (except

for the 1.544 MHz output)

DPLL provides holdover, freerun and jitter

attenuation features with four independent

reference source inputs

Exceptional input clock cycle to cycle variation

tolerance (20 ns for all rates)

DD_CORE

DD_IO

DD_COREA

DD_IOA

July 2005

Ordering Information

ZL50015GAC

ZL50015QCC

ZL50015QCC1

*Pb

256 Ball PBGA

256 Lead LQFP

256 Lead LQFP*

Free Matte Tin

Trays

鈥?/div>

-40擄C to +85擄C

鈥?/div>

Output streams can be configured as bi-

directional for connection to backplanes

Per-stream input and output data rate conversion

selection at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps

or 16.384 Mbps. Input and output data rates can

differ

Per-stream high impedance control outputs

(STOHZ) for 8 output streams

Per-stream input bit delay with flexible sampling

point selection

RESET

ODE

鈥?/div>

STi[15:0]

FPi

CKi

MODE_4M0

MODE_4M1

REF0

REF1

REF2

REF3

REF_FAIL0

REF_FAIL1

REF_FAIL2

REF_FAIL3

S/P Converter

Data Memory

P/S Converter

STio[15:0]

Input Timing

Connection Memory

Output HiZ

Control

STOHZ[7:0]

DPLL

Output Timing

FPo[3:0]

CKo[5:0]

FPo_OFF[2:0]

OSC_EN

OSC

Internal Registers &

Microprocessor Interface

Test Port

OSCo

DS_RD

R/W_WR

Figure 1 - ZL50015 Functional Block Diagram

Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,

France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

MOT_INTEL

DTA_RDY

D[15:0]

A[13:0]

OSCi

TRST

TDi

TMS

TCK

IRQ

TDo

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