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ZL50011/GDC Datasheet

  • ZL50011/GDC

  • Flexible 512 Channel DX with on-chip DPLL

  • 762.49KB

  • 83頁(yè)

  • ZARLINK   ZARLINK

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ZL50011
Flexible 512 Channel DX with on-chip
DPLL
Data Sheet
Features
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512 channel x 512 channel non-blocking switch at
2.048 Mbps, 4.096 Mbps or 8.192 Mbps
operation
Rate conversion between the ST-BUS inputs and
ST-BUS outputs
Integrated Digital Phase-Locked Loop (DPLL)
meets Telcordia GR-1244-CORE Stratum 4
specifications
DPLL provides reference monitor, jitter
attenuation and free run functions
Per-stream ST-BUS input with data rate selection
of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps
Per-stream ST-BUS output with data rate
selection of 2.048 Mbps, 4.096 Mbps or
8.192 Mbps; the output data rate can be different
than the input data rate
Per-stream high impedance control output for
every ST-BUS output with fractional bit
advancement
Per-stream input channel and input bit delay
programming with fractional bit delay
Ordering Information
ZL50011/QCC
ZL50011/GDC
160 Pin LQFP
144 Ball LBGA
July 2005
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V
SS
Per-stream output channel and output bit delay
programming with fractional bit advancement
Multiple frame pulse outputs and reference clock
outputs
Per-channel constant throughput delay
Per-channel high impedance output control
Per-channel message mode
Per-channel Pseudo Random Bit Sequence
(PRBS) pattern generation and bit error detection
Control interface compatible to Motorola non-
multiplexed CPUs
Connection memory block programming capability
IEEE-1149.1 (JTAG) test port
3.3 V I/O with 5 V tolerant input
RESET
ODE
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V
DD
STi0-15
S/P Converter
Data Memory
P/S Converter
STo0-15
FPi
CKi
Input Timing
Connection Memory
Output HiZ Control
STOHZ0-15
REF
DPLL
Microprocessor
Interface
and
Internal
Output Timing
FPo0
CKo0
FPo1
CKo1
FPo2
CKo2
Registers
OSC
APLL
Test Port
IC0 - 4
CLKBYPS
ICONN1
V
DD_APLL
V
SS_APLL
DTA
D15 - 0
A11 - 0
XTALo
XTALi
Figure 1 - ZL50011 Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
TRST
TDO
TMS
SG1
TM1
TM2
R/W
TCK
DS
CS
TDI

ZL50011/GDC相關(guān)型號(hào)PDF文件下載

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  • 英文版
    Flexible 512 Channel DX with Enhanced DPLL
    ZARLINK [Z...
  • 英文版
    Flexible 512 Channel DX with on-chip DPLL
    ZARLINK [Z...
  • 英文版
    Flexible 512-ch Digital Switch
    ZARLINK
  • 英文版
    Flexible 512-ch Digital Switch
    ZARLINK [Z...
  • 英文版
    Enhanced 1 K Digital Switch with Stratum 4E DPLL
    ZARLINK
  • 英文版
    Enhanced 1 K Digital Switch with Stratum 4E DPLL
    ZARLINK [Z...
  • 英文版
    Enhanced 1 K Digital Switch
    ZARLINK [Z...
  • 英文版
    1 K Digital Switch
    ZARLINK [Z...
  • 英文版
    2 K Digital Switch with Enhanced Stratum 3 DPLL
    ZARLINK
  • 英文版
    2 K Digital Switch with Enhanced Stratum 3 DPLL
    ZARLINK [Z...
  • 英文版
    Enhanced 2 K Digital Switch with Stratum 4E DPLL
    ZARLINK
  • 英文版
    Enhanced 2 K Digital Switch with Stratum 4E DPLL
    ZARLINK [Z...
  • 英文版
    Enhanced 2 K Digital Switch
    ZARLINK [Z...
  • 英文版
    Enhanced 4 K Digital Switch with Stratum 3 DPLL
    ZARLINK [Z...
  • 英文版
    Enhanced 4 K Digital Switch with Stratum 4E DPLL
    ZARLINK
  • 英文版
    Enhanced 4 K Digital Switch with Stratum 4E DPLL
    ZARLINK [Z...
  • 英文版
    Enhanced 4 K Digital Switch
    ZARLINK
  • 英文版
    Enhanced 4 K Digital Switch
    ZARLINK [Z...
  • 英文版
    Flexible 4 K x 2 K Channel Digital Switch with H.110 Interfa...
    ZARLINK
  • 英文版
    Flexible 4 K x 2 K Channel Digital Switch with H.110 Interfa...
    ZARLINK [Z...

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