音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

ZL30415GGC Datasheet

  • ZL30415GGC

  • SONET/SDH Clock Multiplier PLL

  • 349.17KB

  • 23頁

  • ZARLINK   ZARLINK

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預覽

ZL30415
SONET/SDH Clock Multiplier PLL
Data Sheet
Features
鈥?/div>
鈥?/div>
鈥?/div>
Meets jitter requirements of Telcordia GR-253-
CORE for OC-12, OC-3, and OC-1 rates
Meets jitter requirements of ITU-T G.813 for STM-
4, and STM-1 rates
Provides one differential LVPECL output clock
selectable to 19.44 MHz, 38.88 MHz, 77.76 MHz,
155.52 MHz, or 622.08 MHz
Provides a single-ended CMOS output clock at
19.44 MHz
Accepts a single-ended CMOS reference at
19.44 MHz or a differential LVDS, LVPECL, or
CML reference at 19.44 MHz or 77.76 MHz
Provides a LOCK indication
3.3 V supply
Ordering Information
ZL30415GGC
64 Ball CABGA
November 2004
-40擄C to +85擄C
鈥?/div>
鈥?/div>
Description
The ZL30415 is an analog phase-locked loop (APLL)
designed to provide jitter attenuation and rate
conversion for SDH (Synchronous Digital Hierarchy)
and SONET (Synchronous Optical Network)
networking equipment. The ZL30415 generates low
jitter output clocks that meet the jitter requirements of
Telcordia GR-253-CORE OC-12, OC-3, OC-1 rates
and ITU-T G.813 STM-4 and STM-1 rates.
The ZL30415 accepts a CMOS compatible reference
at 19.44 MHz or a differential LVDS, LVPECL, or CML
reference at 19.44 MHz or 77.76 MHz and generates a
differential LVPECL output clock selectable to
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, or
622.08 MHz, and a single-ended CMOS clock at
19.44 MHz. The ZL30415 provides a lock indication.
鈥?/div>
鈥?/div>
Applications
鈥?/div>
SONET/SDH line cards
REF_SEL
LPF
FS3
FS2 FS1
C19o, C38o, C77o,
C155o, C622o,
LVPECL output
C19i
Reference
Selection
MUX
Frequency
& Phase
Detector
Loop
Filter
VCO
REFinP/N
19.44 MHz and 77.76 MHz
State
Machine
Reference
and
Bias Circuit
Frequency
Dividers
and
Clock
Drivers
OC-CLKoP/N
C19o
C19i or C77i
CML, LVDS,
LVPECL input
REF_FREQ
LOCK
BIAS
VCC
GND
VDD
C19oEN
03
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.

ZL30415GGC 產(chǎn)品屬性

  • 0現(xiàn)貨

  • 停產(chǎn)

  • -

  • 托盤

  • 停產(chǎn)

  • Not Verified

  • SONET/SDH

  • CML,CMOS,LVDS,LVPECL

  • CMOS,LVPECL

  • 1

  • 3:2

  • 是/是

  • 622.08MHz

  • 3V ~ 3.6V

  • -40°C ~ 85°C

  • 表面貼裝型

  • 64-LFBGA

  • 64-CSPBGA(8x8)

ZL30415GGC相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    T1/E1 System Synchronizer
    ZARLINK
  • 英文版
    T1/E1 System Synchronizer
    ZARLINK [Z...
  • 英文版
    T1/E1 Stratum 3 System Synchronizer
    ZARLINK
  • 英文版
    T1/E1 Stratum 3 System Synchronizer
    ZARLINK [Z...
  • 英文版
    T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for D...
    ZARLINK
  • 英文版
    T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for D...
    ZARLINK [Z...
  • 英文版
    T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for A...
    ZARLINK
  • 英文版
    T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for A...
    ZARLINK [Z...
  • 英文版
    SONET/SDH/PDH Network Interface DPLL
    ZARLINK
  • 英文版
    SONET/SDH/PDH Network Interface DPLL
    ZARLINK [Z...
  • 英文版
    GbE Line Card Synchronizer
    ZARLINK [Z...
  • 英文版
    Network Interface DPLL
    ZARLINK
  • 英文版
    Network Interface DPLL
    ZARLINK [Z...
  • 英文版
    DS1/E1 System Synchronizer with 19.44 MHz Output
    ZARLINK
  • 英文版
    DS1/E1 System Synchronizer with 19.44 MHz Output
    ZARLINK [Z...
  • 英文版
    Telecom Rate Conversion DPLL
    ZARLINK [Z...
  • 英文版
    POTS Line Card PLL
    ZARLINK [Z...
  • 英文版
    SONET/SDH OC-48/OC-192 System Synchronizer
    ZARLINK [Z...
  • 英文版
    SONET/SDH OC-48/OC-192 Line Card Synchronizer
    ZARLINK [Z...
  • 英文版
    Low Jitter Line Card Synchronizer
    ZARLINK [Z...

掃碼下載APP,
一鍵連接廣大的電子世界。

在線人工客服

買家服務:
賣家服務:
技術(shù)客服:

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號,
第一時間獲取資訊。

建議反饋

聯(lián)系人:

聯(lián)系方式:

按住滑塊,拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見,您的參與是維庫提升服務的動力!意見一經(jīng)采納,將有感恩紅包奉上哦!