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ZL30410 Datasheet

  • ZL30410

  • Multi-service Line Card PLL

  • 38頁

  • ZARLINK   ZARLINK

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ZL30410
Multi-service Line Card PLL
Data Sheet
Features
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Generates clocks for OC-3, STM-1, DS3, E3,
DS2, DS1, E1, 19.44 MHz and ST-BUS
Meets jitter generation requirements for STM-1,
OC-3, DS3, E3, J2 (DS2), E1 and DS1 interfaces
Compatible with GR-253-CORE SONET stratum
3 and G.813 SEC timing compliant clocks
Provides 鈥渉it-less鈥?reference switching
Detects frequency of both reference clocks and
synchronizes to any combination of 8 kHz, 1.544
MHz, 2.048 MHz and 19.44 MHz reference
frequencies
Continuously monitors both references for
frequency accuracy exceeding 鹵12 ppm
Holdover accuracy of 70x10
-12
meets GR-1244
Stratum 3E and ITU-T G.812 requirements
Meets requirements of G.813 Option 1 for SDH
Equipment Clocks (SEC) and GR-1244 for
Stratum 4E and Stratum 4 Clocks
3.3V power supply
Ordering Information
ZL30410QCC
80 Pin LQFP
November 2003
-40擄C to 85擄C
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Clock generation for ST-BUS and GCI timing
Description
The ZL30410 is a Multi-service Line Card
Phase-Locked Loop designed to generate multiple
clocks for SONET, SDH and PDH equipment including
timing for ST-BUS and GCI interfaces.
The ZL30410 operates in NORMAL (LOCKED),
HOLDOVER and FREE-RUN modes to ensure that in
the presence of jitter and interruptions to the reference
signals, the generated clocks meet international
standards. The filtering characteristics of the PLL are
hardware pin selectable and they do not require any
external adjustable components. The ZL30410 uses an
external 20 MHz Master Clock Oscillator to provide a
stable timing source for the HOLDOVER operation.
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Applications
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Line Card synchronization for SDH, SONET, DS3,
E3, J2 (DS2), E1 and DS1 interfaces
Timing card synchronization for SDH and PDH
Network Elements
VDD GND
C20i
FCS
OE
PRI
PRIOR
Primary
Acquisition
PLL
Master Clock
Frequency
Calibration
APLL
MUX
SEC
SECOR
RefSel
RESET
Core PLL
Clock
Synthesizer
Secondary
Acquisition
PLL
C155P/N
C34/C44
C19o
C16o
C8o
C6o
C4o
C2o
C1.5o
F16o
F8o
F0o
E3DS3/OC3
E3/DS3
Control State Machine
JTAG
IEEE
1149.1a
Tclk
Tdi
Tdo
Tms
Trst
07
MS1 MS2
RefAlign
LOCK
HOLDOVER
Figure 1 - Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.

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