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ZL30106 Datasheet

  • ZL30106

  • SONET/SDH/PDH Network Interface DPLL

  • 421.04KB

  • 48頁

  • ZARLINK   ZARLINK

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ZL30106
SONET/SDH/PDH
Network Interface DPLL
Data Sheet
Features
鈥?/div>
鈥?/div>
Synchronizes to clock-and-sync-pair to maintain
minimal phase skew between inputs and outputs
Supports output wander and jitter generation
specifications for SONET/SDH and PDH
interfaces
Accepts three input references and synchronizes
to any combination of 2 kHz, 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
inputs
Provides a range of clock outputs:
- 2.048 MHz (E1), 16.384 MHz and either
4.096 MHz and 8.192 MHz or 32.768 MHz and
65.536 MHz
-
-
-
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
19.44 MHz (SONET/SDH)
1.544 MHz (DS1) and 3.088 MHz
a choice of 6.312 MHz (DS2), 8.448 MHz (E2),
44.736 MHz (DS3) or 34.368 MHz (E3)
鈥?/div>
鈥?/div>
Ordering Information
ZL30106QDG 64 pin TQFP
-40擄C to +85擄C
鈥?/div>
鈥?/div>
Selectable loop filter bandwidth of 29 Hz or
922 Hz
Less than 24 ps
rms
intrinsic jitter on the
19.44 MHz output clock, compliant with GR-253-
CORE OC-3 and G.813 STM-1 specifications
Less than 0.6 ns
pp
intrinsic jitter on all PDH output
clocks and frame pulses
Selectable external master clock source: clock
oscillator or crystal
Simple hardware control interface
October 2004
鈥?/div>
鈥?/div>
鈥?/div>
Provides 5 styles of 8 kHz framing pulses and a
2 kHz multi-frame pulse
Provides automatic entry into Holdover and return
from Holdover
Manual and automatic hitless reference switching
Provides lock, holdover and accurate reference
fail indication
OSCi
OSCo
TIE_CLR
Applications
鈥?/div>
鈥?/div>
鈥?/div>
Line card synchronization for SONET/SDH and
PDH systems
Wireless base-station Network Interface Card
AdvancedTCA鈩?and H.110 line cards
BW_SEL
LOCK
OUT_SEL2
REF0
REF_SYNC0
REF1
REF_SYNC1
REF2
REF_FAIL0
REF_FAIL1
REF_FAIL2
APP_SEL1:0
Master Clock
MUX
TIE
Corrector
Circuit
Virtual
Reference
DPLL
E1
Synthesizer
Reference
Monitor
TIE
Corrector
Enable
DS1
Synthesizer
Mode
Control
SDH
Synthesizer
Programmable
Synthesizer
REF_SEL1:0
RST
State Machine
Frequency
Select
MUX
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
C1.5o
C3o
C19o
F2ko
C6/8.4/34/44o
OUT_SEL1:0
IEEE
1149.1a
TRST
MODE_SEL1:0
HMS
HOLDOVER
TCK
TDI TMS TDO
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.

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