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ZL10310 Datasheet

  • ZL10310

  • Digital Television DVB-T-On-a-Chip Processor

  • 644.87KB

  • 40頁(yè)

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ZL10310/ZL10311
Digital Television DVB-T-On-a-Chip
Processor
Data Sheet
Features
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DTV-SoC for Digital Terrestrial Television (DTT)
On-chip DVB-T COFDM demodulator with FEC.
6 Video DACs on-chip, for Composite or
Component (RGB or Y U/V) Analog Video
Twin PAL/NTSC DENCs
Low Power (<1.4W Typical)
Low Component Count
Unified SDRAM controller
I
2
S Digital Audio Input
I
2
S and S/PDIF Digital Audio outputs
MPEG-2 Audio & Video decoders
PowerPC 405
TM
CPU Core with 16k/16k cache,
Memory manager and Virtual memory system
Complete Linux-based Software Development Kit
(SDK)
IDE interface
Inputs for external MPEG-2 Transport Streams,
allowing support for external demodulators (e.g.
Cable TV, Satellite TV)
Conditional Access (CA) DVB-descrambler
Issue 1.0
November 2002
Ordering Information
ZL10310/GAC
ZL10311/GAC
388 ball EPBGA
388 ball EPBGA
0
0
C to +70
0
C
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Smart Card Interface
Infrared & UART interface
DVB-compatible Common Interface (CI) control
and bitstream interfaces
Multi-stream multiplexing to support internal and
external demodulators
External Modem support interface
Supports Macrovision
TM
Copy Protection -
(ZL10311
only; available to Macrovision license
holders only)
Dolby
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Digital* Decoding
- (ZL10311 only;
available to Dolby
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Digital* license holders only -
*awaiting certification)
Bitstream
O/P
/Second Bitstream
I/P
Smart Card
Stereo Audio
2
I S DAC
S/PDIF
ZL10310 / ZL10311 DTV-SOC
De-mod
/JTAG
EXTIN
JTAG
Audio
Decoder
Bitstream
Multiplexing &
Control
De-
scrambler
System
DeMultiplex
ADC IN
/De-mod
AGC B
Flash
IDE
CI Control
Smart Card
CODEC/modem
2
IC
UART/IRDA
BIT I/O
ADCIN
COFDM
DeModulator
& FEC
Video
Decoder
AUX Bus
Video Scaler
/ Blender
Cached
PowerPC 405
Sub System
R
Comp
Peripherals
Video
Video
DENCs
/DACs
8k Boot
ROM
SDRAM
Controller
SDRAM
Controller
Y+U/V
RGB
Analog
Video
Power Management
SDRAM 1
BUS
SDRAM 0
BUS
(optional)
Figure 1 - Block Diagram of ZL10310 and ZL10311
1

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