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180MHz Clock Support
150ps Maximum Output to Output Skew
TM
Supports PowerPC , Intel and RISC Processors
11 Clock Outputs: Frequency Configurable
Outputs Drive up to 22 Clock Lines
LVCMOS/LVTTL Compatible Inputs
Output Tri-state Control
Spread Spectrum Compatible
3.3V Power Supply
Pin Compatible with MPC952
Industrial Temp. Range: -40擄C to +85擄C
32-Pin TQFP Package
Frequency Table
VCO_SEL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL (A:C)
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
QA(0:4)
VCO/4
VCO/4
VCO/4
VCO/4
VCO/6
VCO/6
VCO/6
VCO/6
VCO/8
VCO/8
VCO/8
VCO/8
VCO/12
VCO/12
VCO/12
VCO/12
Table 1
QB(0:3)
VCO/4
VCO/4
VCO/2
VCO/2
VCO/4
VCO/4
VCO/2
VCO/2
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
QC (0,1)
VCO/2
VCO/4
VCO/2
VCO/4
VCO/2
VCO/4
VCO/2
VCO/4
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
Block Diagram
PLL_EN#
REFCLK
FB_IN
LPF
Phase
Detector
VCO
200-480M
/2
/4,
/6
QA0
QA1
QA2
QA3
QA4
Pin Configuration
VCO_SEL
SELA
/4,
/2
VDDC
QB0
QB1
32
31
30
29
28
27
26
SELB
QB2
QB3
/2,
/4
QC0
QC1
9
10
11
12
13
14
15
PLL_EN#
QA0
VSS
QA1
VDDA
QA2
Figure 1
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07085 Rev. *A
VDDC
VDD
16
SELC
MR/OE#
VCO_SEL
SELC
SELB
SELA
MR/OE#
REFCLK
VSS
FB_IN
1
2
3
4
5
6
7
8
25
24
23
22
21
20
19
18
17
VDDC
QC1
QC0
QB3
QB2
VSS
VSS
Z9952
VSS
QB1
QB0
VDDC
VDDC
QA4
QA3
VSS
06/18/2001
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