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180MHz Clock Support
TM
Supports PowerPC , Intel and RISC Processors
9 Clock Outputs: Frequency Configurable
Two Reference Clock Inputs for Dynamic Toggling
Oscillator or PECL Reference Input
Output Disable Control
Spread Spectrum Compatible
3.3V Power Supply
Pin Compatible with MPC951
Industrial Temp. Range: -40擄C to +85擄C
32-Pin TQFP Package
Frequency Table
SEL (A:D)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
QA
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
QB
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/8
VCO/8
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/8
VCO/8
Table 1
VCO
200-
480MHz
QC (0,1)
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
QD (0:4)
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
Block Diagram
SELA
PLL_EN
TCLK
REF_SEL
PECL_CLK
PECL_CLK#
Phase
Detector
2/ 4
QA
Pin Configuration
REF_SEL
LPF
4/ 8
QB
PLL_EN
VDDC
27
TCLK
VSS
FB_IN
SELB
SELC
MR/OE#
4/ 8
QC0
32
31
30
29
28
26
Power-On Reset
4/ 8
QD0
QD1
SELD
QD2
QD3
QD4
VDD
FB_IN
SELA
SELB
SELC
SELD
VSS
PECL_CLK
1
2
3
4
5
6
7
8
9
25
24
23
22
21
20
19
18
17
16
QC1
VSS
QA
QB
Z9951
10
11
12
13
14
15
QC0
VDDC
QC1
VSS
QD0
VDDC
QD1
VSS
PECL_CLK#
QD4
VSS
QD3
MR/OE#
VDDC
Figure 1
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07084 Rev. *A
VDDC
QD2
06/18/2001
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