P
RELIMINARY
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
Z89320
16-B
IT
DSP D
IGITAL
S
IGNAL
P
ROCESSOR
GENERAL DESCRIPTION
The Z89320 is a second generation, 16-bit fractional, two鈥檚
complement CMOS Digital Signal Processor (DSP). Most
instructions, including multiply and accumulate, are
accomplished in a single clock cycle. The processor
contains 1Kbyte of on-chip data RAM (two blocks of 256
16-bit words), 4K words of program ROM. Also, the
processor features a 24-bit ALU, a 16x16 multiplier, a 24-
bit Accumulator and a shifter. Additionally, the processor
contains a six-level stack, three vectored interrupts and
two inputs for conditional program jumps. Each RAM block
contains a set of three pointers which may be incremented
or decremented automatically to affect hardware looping
without software overhead. The data RAMs can be
simultaneously addressed and loaded to the multiplier for
a true single cycle multiply.
The device includes a 16-bit I/O bus for transferring data
or for mapping peripherals into the processor address
space. Additionally, there are two general purpose user
inputs and two user outputs. Operation with slow peripherals
is accompished with a ready input pin.
Development tools for the IBM PC include a relocatable
assembler, a linker loader, and an ANSI-C compiler. Also,
the development tools include a simulator/debugger, a
cross assembler for the TMS320 family assembly code
and a hardware emulator.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Power
Ground
Circuit
V
CC
GND
Device
V
DD
V
SS
DC-4128-00
(12-2-92)
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