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Z80230 Datasheet

  • Z80230

  • ESCC⑩ ENHANCED SERIAL COMMUNICATION CONTROLLER

  • 12頁

  • ZILOG   ZILOG

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C
USTOMER
P
ROCUREMENT
S
PECIFICATION
Z80230
ESCC
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E
NHANCED
S
ERIAL
C
OMMUNICATION
C
ONTROLLER
GENERAL DESCRIPTION
The Zilog Enhanced Serial Communications Controller,
Z80230 ESCC, is a pin and software compatible CMOS
member of the SCC family introduced by Zilog in 1981. The
ESCC is a dual-channel, full-duplex data communications
controller capable of supporting a wide range of popular
protocols. The ESCC is built from Zilog鈥檚 industry standard
SCC core and is compatible with designs using Zilog鈥檚
SCC to receive and transmit data. It has many improve-
ments that significantly reduce CPU overhead. The addi-
tion of a 4-byte transmit FIFO and an 8-byte receive FIFO
significantly reduces the overhead required to provide
data to, and get data from, the transmitters and receivers.
The ESCC also has many features that improve packet
handling in SDLC mode. The ESCC will automatically:
transmit a flag before the data, reset the Tx Underrun/EOM
latch, force the TxD pin high at the appropriate time when
using NRZI encoding, deassert the /RTS pin after the
closing flag, and better handle ABORTed frames when
using the 10x19 status FIFO. The combination of these
features along with the deeper data FIFOs significantly
simplifies SDLC driver software.
The CPU hardware interface has been simplified by reliev-
ing the databus setup time requirement and supporting
the software generation of the interrupt acknowledge sig-
nal (INTACK). These changes allow an interface with less
external logic to many microprocessor families while main-
taining compatibility with existing designs. I/O handling of
the ESCC is improved over the SCC with faster response
of the /INT and /DTR//REQ pins.
The many enhancements added to the ESCC permits a
system design that increases overall system performance
with better data handling and less interface logic.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Power
Ground
Circuit
V
CC
GND
Device
V
DD
V
SS
DC-4021-05
(7-07-92)
1

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