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XRT83L30 Datasheet

  • XRT83L30

  • SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVER...

  • 431.79KB

  • 78頁

  • EXAR   EXAR

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謾莽
MAY 2003
PRELIMINARY
XRT83L30
REV. P1.3.0
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
GENERAL DESCRIPTION
The XRT83L30 is a fully integrated single-channel
long-haul and short-haul line interface unit for
T1(1.544Mbps) 100鈩? E1(2.048Mbps) 75鈩?or 120鈩?/div>
and J1 110鈩?applications.
In long-haul applications the XRT83L30 accepts sig-
nals that have passed through cables from 0 feet to
over 6000 feet in length and have been attenuated by
0 to 45dB at 772kHz in T1 mode or 0 to 43dB at
1024kHz in E1 mode. In T1 applications, the
XRT83L30 can generate five transmit pulse shapes to
meet the short-haul Digital Cross-Connect (DSX-1)
template requirements as well as for Channel Service
Units (CSU) Line Build Out (LBO) filters of 0dB,
-7.5dB, -15dB and -22.5dB as required by FCC rules.
It also provides programmable transmit pulse genera-
tor that can be used for arbitrary output pulse shaping
allowing performance improvement over a wide vari-
ety of conditions.
The XRT83L30 provides both Serial Host micropro-
cessor interface and Hardware Mode for program-
ming and control. Both B8ZS and HDB3 encoding
and decoding functions are included and can be dis-
abled as required. On-chip crystal-less jitter attenua-
tor with a 32 or 64 bit FIFO can be placed either in the
receive or the transmit path with loop bandwidths of
less than 3Hz. The XRT83L30 provides a variety of
loop-back and diagnostic features as well as transmit
driver short circuit detection and receive loss of signal
monitoring. It supports internal impedance matching
for 75鈩? 100鈩? 110鈩?and 120鈩?for both transmitter
and receiver. For the receiver this is accomplished by
internal resistors or through the combination of one
single fixed value external resistor and programmable
internal resistors. In the absence of the power supply,
the transmit output and receive input are tri-stated al-
lowing for redundancy applications. The chip includes
an integrated programmable clock multiplier that can
synthesize T1 or E1 master clocks from a variety of
external clock sources.
APPLICATIONS
鈥?/div>
T1 Digital Cross-Connects (DSX-1)
鈥?/div>
ISDN Primary Rate Interface
鈥?/div>
CSU/DSU E1/T1/J1 Interface
鈥?/div>
T1/E1/J1 LAN/WAN Routers
鈥?/div>
Public switching Systems and PBX Interfaces
鈥?/div>
T1/E1/J1 Multiplexer and Channel Banks
FEATURES
(See Page 2)
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT83L30 T1/E1/J1 LIU (H
OST
M
ODE
)
MCLKE1
MCLKT1
TXTEST[0:2]
INSBPV
TPOS / TDATA
TNEG / CODES
TCLK
MASTER CLOCK SYNTHESIZER
MCLKOUT
TAOS
ENABLE
QRSS
PATTERN
GENERATOR
HDB3/
B8ZS
ENCODER
TX FILTER
& PULSE
SHAPER
LBO[3:0]
JA
SELECT
QRSS ENABLE
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
LOOPBACK
ENABLE
TIMING &
DATA
RECOVERY
AIS
DETECTOR
PEAK
DETECTOR
& SLICER
DRIVE
MONITOR
TIMING
CONTROL
LINE
DRIVER
DMO
TTIP
TRING
TX/RX JITTER
ATTENUATOR
LOCAL
ANALOG
LOOPBACK
TXON
QRPD
RCLK
RNEG / LCV
RPOS / RDATA
NLCD
RLOS
QRSS
DETECTOR
HDB3/
B8ZS
DECODER
NETWORK
LOOP
DETECTOR
TX/RX JITTER
ATTENUATOR
RX
EQUALIZER
RTIP
RRING
NLCD ENABLE
LOS
DETECTOR
EQUALIZER
CONTROL
AISD
TEST
HW/HOST
CS
INT
Serial Interface
ICT
SDO
SCLK
SDI
RESET
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
鈥?/div>
(510) 668-7000
鈥?/div>
FAX (510) 668-7017
鈥?/div>
www.exar.com

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