謾莽
JUNE 2001
XRT82L34
REV. 1.1.0
QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
GENERAL DESCRIPTION
The XRT82L34 is a fully integrated Quad (four chan-
nels) short-haul line interface unit for T1(1.544Mbps)
100鈩?and E1(2.048Mbps) 75鈩?or 120鈩?applications.
Each channel consists of a receiver with equalizer for
reliable data and clock recovery, and a transmitter
which accepts either single or dual-rail digital inputs
for signal transmission to the line using a low output
impedance line driver. The device also includes a
crystal-less jitter attenuator which, depending on sys-
tem requirements, can be selected in the receive or
transmit path through the Host or Hardware Mode
control.
XRT82L34 is a low power CMOS device operating on
a single 3.3V supply with 5V tolerant digital inputs.
FEATURES
鈥?/div>
Fully integrated quad, short-haul PCM transceivers
for E1 and T1 applications.
鈥?/div>
On Chip Receive Equalizer and Transmit Pulse
Shaper for DS1 Digital Cross Connect (DSX-1) and
CEPT 75鈩?and 120鈩?line terminations
鈥?/div>
On chip clock recovery circuit
鈥?/div>
Transformer or capacitor coupled receiver inputs
鈥?/div>
Crystal-less jitter attenuator can be selected in the
transmit or receive path
鈥?/div>
High receiver interference immunity
鈥?/div>
Per-channel transmit power shutdown
鈥?/div>
Tri-state transmit output capability
鈥?/div>
On chip per-channel driver failure monitoring circuit
鈥?/div>
On chip HDB3/B8ZS/AMI encoder/decoder func-
tions
鈥?/div>
Transmit return loss meets or exceeds ETSI 300
166 standard
鈥?/div>
Meets or exceeds specifications in ITU G.703,
G.775, G.736 and G.823; Bellcore GR-499-CORE;
ANSI T1.403 and ETSI 300-166
鈥?/div>
3.3V or 5.0V Logic level inputs
鈥?/div>
Single +3.3V Supply Operation
APPLICATIONS
鈥?/div>
Digital cross connects (DSX-1)
鈥?/div>
Channel Banks
鈥?/div>
High speed data transmission line cards
鈥?/div>
T1/E1 Multiplexer
鈥?/div>
Public switching systems and PBX interfaces
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT82L34 T1/E1/J1 LIU (H
OST
M
ODE
)
Driver
Monitor
TVDD[n]
TxClk[n]
TxPOS[n]/TDATA[n]
TxNEG[n]
HDB3/
B8ZS
Encoder
MUX
Tx/Rx Jitter
Attenuator
Tx Timing
Control
Tx Pulse
Shaper
Line
Driver
TTIP[n]
TRing[n]
Enable/
Disable
Remote
LoopBack
Digital
LoopBack
Clock
Generator
Local
Analog
LoopBack
TGND[n]
MClk
Peak
Detector
& Slicer
Rx
Equalizer
RxClk[n]
RxPOS[n]/RDATA[n]
RxNEG[n]/LCV[n]
HDB3/
B8ZS
Decoder
MUX
Tx/Rx Jitter
Attenuator
Timing & Data
Recovery
RTIP[n]
RRing[n]
RxLOS[n]
Channel 0
Channel 1
Channel 2
Channel 3
LOS
Detect
INT
RDY_DTACK
PClk/Codes
PTS1/ClkE
PTS2/SR_DR
Reset
ICT
碌
P Controller & Hardware Interface
Test
ADD [0:3]
D[0:7]
WR_R/W/TxOFF0
ALE_AS/TxOFF2
CS/TxOFF3
RD_DS/TxOFF1
HW/HOST
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
鈥?/div>
(510) 668-7000
鈥?/div>
FAX (510) 668-7017
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