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XRT73LC00IV Datasheet

  • XRT73LC00IV

  • E3/DS3/STS-1 LINE INTERFACE UNIT

  • 53頁

  • EXAR   EXAR

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謾莽
AUGUST 2002
PRELIMINARY
XRT73LC00
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.1
GENERAL DESCRIPTION
The XRT73LC00 DS3/E3/STS-1 Line Interface Unit is
a low power CMOS version of the XRT73L00A and
consists of a line transmitter and receiver integrated
on a single chip and is designed for DS3, E3 or SO-
NET STS-1 applications.
XRT73LC00 can be configured to support the E3
(34.368 Mbps), DS3 (44.736 Mbps) or the SONET
STS-1 (51.84 Mbps) rates.
In the transmit direction, the XRT73LC00 encodes in-
put data to either B3ZS (for DS3/STS-1 applications)
or HDB3 (for E3 applications) format and converts the
data into the appropriate pulse shapes for transmis-
sion over coaxial cable via a 1:1 transformer.
In the receive direction the XRT73LC00 performs
equalization on incoming signals, performs Clock Re-
covery, decodes data from either B3ZS or HDB3 for-
mat, converts the receive data into TTL/CMOS for-
mat, checks for LOS or LOL conditions and detects
and declares the occurrence of line code violations.
The XRT73LC00 also contains a 4-Wire Microproces-
sor Serial Interface for accessing the on-chip Com-
mand registers.
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT73LC00
E3
S T S -1 /D S 3
H o s t/(H W )
FEATURES
鈥?/div>
Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L00A
鈥?/div>
Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
鈥?/div>
Full Loop-Back Capability
鈥?/div>
Transmit and Receive Power Down Modes
鈥?/div>
Full Redundancy Support
鈥?/div>
Contains a 4-Wire Microprocessor Serial Interface
鈥?/div>
Uses Minimum External components
鈥?/div>
Low Power CMOS Design
鈥?/div>
Single +3.3V Power Supply
鈥?/div>
5 V Tolerant pins
鈥?/div>
-40擄C to +85擄C Operating Temperature Range
鈥?/div>
Available in a 44 pin TQFP package
APPLICATIONS
鈥?/div>
Interfaces to E3, DS3 or SONET STS-1 Networks
鈥?/div>
CSU/DSU Equipment
鈥?/div>
PCM Test Equipment
鈥?/div>
Fiber Optic Terminals
鈥?/div>
Multiplexers
RLO L EXCLK
IC T
R C L K IN V
R T IP
R R IN G
AGC/
E qualizer
S licer
C lock
R ecovery
RCLK1
Invert
L C V /(R C L K 2 )
R E Q D IS
P eak
D etecto r
LO S D etector
D ata
R ecovery
H D B 3/
B 3Z S
D ecode r
RPOS
RNEG
LOSTHR
SDI
S D O /(L C V )
S C lk
CS
REGRESET
D R /S R
S erial
P rocesso r
Interface
RLO S
Loop M U X
LLB
RLB
E N D E C D IS
TAOS
T T IP
P ulse
S haping
T R IN G
H D B 3/
B 3Z S
E ncoder
Tra nsm it
Logic
D uty C ycle A dju st
TPD ATA
TND ATA
T C lk
M T IP
M R IN G
DMO
D evice
M onitor
Tx
C ontro l
TXLEV
TXO FF
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
鈥?/div>
(510) 668-7000
鈥?/div>
FAX (510) 668-7017
鈥?/div>
www.exar.com

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