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XRT73L03IVS Datasheet

  • XRT73L03IVS

  • Telecommunication IC

  • 69頁

  • ETC

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謾莽
MAY 2000
ADVANCED CONFIDENTIAL
XRT73L03
REV. A1.0.7
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
GENERAL DESCRIPTION
The XRT73L03, 3-Channel, E3/DS3/STS-1 Line In-
terface Unit consists of three independent line trans-
mitters and receivers integrated on a single chip, de-
signed for E3, DS3 or SONET STS-1 applications.
Each channel within the XRT73L03 device can be
configured to support the E3 (34.368 Mbps), DS3
(44.736 Mbps) or the SONET STS-1 (51.84 Mbps)
rates. Each channel can be configured to operate in
a mode/data rate that is independent of the other
channels.
In the transmit direction, each channel within the
XRT73L03 will encode input data to either B3ZS or
HDB3 format and convert the data into the appropri-
ate pulse shapes for transmission over coaxial cable
via a 1:1 transformer.
In the receive direction, the XRT73L03 can perform
Equalization on incoming signals, perform Clock Re-
covery, decode data from either B3ZS or HDB3 for-
mat, convert the receive data into TTL/CMOS format,
check for LOS or LOL conditions and detect and de-
clare the occurrence of Line code Violations.
XRT73L03 BLOCK DIAGRAM
E3_Ch(n)
STS-1/DS3_Ch(n)
Host/(HW)
RLOL(n)
EXClk(n)
RxOFF(n)
RxClkINV
APPLICATIONS
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Digital Cross Connect Systems
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CSU/DSU Equipment
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Routers
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Fiber Optic Terminals
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Multiplexers
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ATM Switches
FEATURES
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Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
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Contains a 4-Wire Microprocessor Serial Interface
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Full Loop-back Capability
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Transmit and Receive Power Down Modes
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Full Redundancy Support
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Single +3.3V Power Supply
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Uses Minimum External components
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-40擄C to +85擄C Operating Temperature Range
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Available in a 120 pin TQFP package
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5V tolerant I/O
RTIP(n)
RRing(n)
REQEN(n)
AGC/
Equalizer
Peak
Detector
Slicer
Clock
Recovery
Data
Recovery
LOS Detecto r
Invert
RxClk(n)
HDB3/
B3ZS
Decoder
RPOS(n)
RNEG(n)
LCV(n)
ENDECDIS
LOSTHR(n)
SDI
SDO
SClk
CS
REGR
Serial
Processor
Interface
RLOS(n)
Loop MUX
LLB(n)
RLB(n)
TAOS(n)
TTIP(n)
Pulse
Shaping
TRing(n)
MTIP(n)
MRing(n)
DMO(n)
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
TPData(n)
TNData(n)
TxClk(n)
TxLEV(n)
Device
Monitor
Channel 1 - (n) = 1
Channel 2 - (n) = 2
Channel 3 - (n) = 3
TxOFF(n)
Notes: 1. (n) = 1, 2 or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in "Host" Mode and redefined in
"Harware" Mode.
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
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(510) 668-7000
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FAX (510) 668-7017
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www.exar.com
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