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XRT7302IV Datasheet

  • XRT7302IV

  • PCM Transceiver

  • 76頁(yè)

  • ETC

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謾莽
AUGUST 2000
XRT7302
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
GENERAL DESCRIPTION
The XRT7302 Dual Channel E3/DS3/STS-1 Trans-
ceiver IC consists of two fully integrated transmitter
and receiver line transceivers designed for E3, DS3
or SONET STS-1 applications.
Each channel within the XRT7302 can be configured
to support the E3 (34.368 Mbps), DS3 (44.736 Mbps)
or the SONET STS-1 (51.84 Mbps) rates. Each chan-
nel can be configured to operate in a mode/data rate
that is independent of the other channel.
In the transmit direction, each channel within the
XRT7302 will encode input data to either B3ZS or
HDB3 format and convert the data into the appropri-
ate pulse shapes for transmission over coaxial cable
via a 1:1 transformer.
In the receive direction, the XRT7302 can perform
Equalization on incoming signals, perform Clock Re-
covery, decode data from either B3ZS or HDB3 for-
mat, convert the receive data into TTL/CMOS format,
check for LOS or LOL conditions and detect and de-
clare the occurrence of Line code Violations.
APPLICATIONS
XRT7302 BLOCK DIAGRAM
E3_Ch(n)
STS-1/DS3_Ch(n)
Host/HW
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Digital Cross Connect Systems
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CSU/DSU Equipment
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Routers
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Fiber Optic Terminals
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Multiplexers
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ATM Switches
FEATURES
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Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
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Contains a 4-Wire Microprocessor Serial Interface
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Full Loop-back Capability
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Transmit and Receive Power Down Modes
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Full Redundancy Support
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Single +5V Power Supply
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Uses Minimum External components
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Operates over -40擄C to +85擄C Temperature Range
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Available in an 80 pin TQFP Thermal Enhanced
package with integral Heat Sink
RLOL(n) ExClk(n)
RxClkINV
RTIP(n)
RRing(n)
REQEN(n)
RxOFF(n)
LOSTHR(n)
SDI
SDO
SClk
CS
REGR
AGC/
Equalizer
Slicer
Clock
Recovery
Data
Recovery
LOS Detecto r
Invert
RxClk(n)
Peak Detector
HDB3/
B3ZS
Decoder
RPOS(n)
RNEG(n)
LCV(n)
ENDECDIS
RLOS(n)
Serial
Processor
Interface
Loop MUX
LLB(n)
RLB(n)
TTIP(n)
TRing(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
TAOS(n)
Transmit
Logic
Duty Cycle Adjust
TPData(n)
TNData(n)
TxClk(n)
TxLEV(n)
TxOFF(n)
Channel 1
MTIP(n)
MRing(n)
DMO(n)
Device
Monitor
Tx
Control
Channel 2
Notes: 1. (n) = 1 or 2 for the respective channel.
2. Serial Processor Interface pins are shared by both Channels in HOST Mode and are redefined in Hardware Mode.
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
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(510) 668-7000
鈥?/div>
FAX (510) 668-7017
鈥?/div>
www.exar.com
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