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XRT72L74IB Datasheet

  • XRT72L74IB

  • Telecommunication IC

  • 37頁(yè)

  • ETC

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APRIL 2000
PRELIMINARY
XRT72L74
REV. P1.0.0
4 CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER IC
GENERAL DESCRIPTION
The XRT72L74 4 Channel DS3 ATM User Network
Interface (UNI)/Clear-Channel Framer device is de-
signed to function as either a DS3 ATM UNI or a DS3
Clear Channel Framer IC. For ATM UNI applications,
this device provides the ATM Physical Layer (Physical
Medium Dependent and Transmission Convergence
sub-layers) interface for the public and private net-
works at DS3 rates. For Clear-Channel Framer appli-
cations, this device supports the transmission and re-
ception of 鈥渦ser data鈥?via the DS3 payload.
The XRT72L74 DS3 ATM UNI/Clear-Channel Framer
incorporates Receive, Transmit, Microprocessor Inter-
face, Performance Monitor, Test and Diagnostic and
Line Interface Unit Scan Drive functional sections.
FEATURES
鈥?/div>
Compliant with UTOPIA Level 1and 2, 8 or 16 Bit,
Interface Specification and supports UTOPIA Bus
operating at 25, 33 or 50 MHz
鈥?/div>
Contains on-chip 16 cell FIFO (configurable in
depths of 4, 8, 12 or 16 cells), in both the Transmit
(TxFIFO) and Receive Directions (RxFIFO)
鈥?/div>
Contains on-chip 54 byte Transmit and Receive
OAM Cell Buffer for transmission, reception and
processing of OAM Cells
鈥?/div>
Supports PLCP or ATM Direct Mapping modes
鈥?/div>
Supports M13 and C-Bit Parity Framing Formats
鈥?/div>
Supports DS3 Clear-Channel Framing Applications
鈥?/div>
Includes PRBS Generator and Receiver
鈥?/div>
Supports Line, Cell, and PLCP Loop-backs
鈥?/div>
Interfaces to 8 or 16 Bit wide Motorola and Intel 碌Ps
and 碌Cs
鈥?/div>
Low power 3.3V, 5V tolerant, CMOS
鈥?/div>
Available in 352 pin PBGA Package
APPLICATIONS
鈥?/div>
Private User Network Interfaces
鈥?/div>
ATM Switches
鈥?/div>
ATM Routers and Bridges
鈥?/div>
ATM Concentrators
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT72L74 DS3 UNI IC
A[8:0]
WR_RW
Rd_DS
CS
ALE_AS
Reset
Int
D[15:0]
Width16
MOTO/Intel
Rdy_Dtck
Microprocessor
Interface
(Programmable
Registers and
Interrupt Block)
Test and Diagnostic
Line I/F Drive and
Scan
Receiver Channel (n)
RxLOS_n
RxOOF_n
RLOS_n
RxAIS_n
RxRed_n
RxOH_n
RxOHClk_n
RxLineClk_n
RxPOS_n
RxNEG_n
RxOHFrame_n
RxFrame_n
RxSerClk_n
RxPOOF_n
RxPFrame_n
RxPOHFrame_n
RxPOH_n
RxPOHClk_n
RxPLOF_n
RxPRed_n
RxLCD_n
RxCellRxed_n
RxGFCClk_n
RxGFCMSn
RxGFC_n
RxUClk
RxUEn
RxUPrty
RxUData[15:0]
RxUSoC
RxUClav
RxUAddr[4:0]
Transmitter Channel (n)
TxPOS_n
TxNEG_n
TxLineClk_n
TxFrame_n
TxOHClk_n
TxOHFrame_n
TxAISEn_n
TxFrameRef_n
TxInClk_n
TxOHIns_n
TxOH_n
TxPOHFrame_n
8KRef_n
StuffCtl_n
TxPFrame_n
TxPOH_n
TxPOHClk_n
TxPOHIns_n
TxGFC_n
TxGFCMSn
TxGFCClk
TxUClk
TxUData[15:0]
TxUPrty
TxUSoC
TxUEn
TxUClav
TxUAddr[4:0]
FEAC
Processor
Channel (n)
Transmit
DS3
Framer
Receive
DS3
Framer
LAPD
Transceiver
Channel (n)
Transmit PLCP
Processor/
Clear Channel
Tx Serial Data
Processor
Transmit Cell
Processor
Performance
Monitor
Channel (n)
Receive PLCP
Processor/
Clear Channel
Rx Serial Data
Processor
Receive Cell
Processor
Tx Utopia
Interface
Note: Typical
channel (n) shown,
where;
n=0, 1, 2 or 3.
Rx Utopia
Interface
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
鈥?/div>
(510) 668-7000
鈥?/div>
FAX (510) 668-7017
鈥?/div>
www.exar.com
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