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XRT71D03IV Datasheet

  • XRT71D03IV

  • Telecommunication IC

  • 24頁

  • ETC

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謾莽
SEPTEMBER 2001
XRT71D03
REV. 1.1.2
3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
GENERAL DESCRIPTION
The XRT71D03 is a three channel, single chip Jitter
Attenuator, that meets the Jitter transfer characteris-
tics requirements specified in the ETSI TBR-24,
Bellcore GR-499 and GR-253 standards.
In addition, the XRT71D03 also meets the Jitter and
Wander specifications described in the ANSI
T1.105.03b 1997, Bellcore GR-253 and GR-499 stan-
dards for Desynchronizing and Pointer adjustments in
the DS3 to STS-SPE mapping applications.
FEATURES
鈥?/div>
Meets the E3/DS3/STS-1 jitter requirements
鈥?/div>
No external components required
鈥?/div>
Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755, GR-235-CORE, GR-
499-CORE,1995 standards
F
IGURE
1. B
LOCK
D
IAGRAM
(
ONE
C
HANNEL
)
鈥?/div>
Meets output jitter requirement as specified by
ETSI TBR24
鈥?/div>
Meets the Jitter and Wander specifications
described in T1.105.03b,GR-253 and GR-499 stan-
dards.
鈥?/div>
Selectable buffer size of 16 and 32 bits
鈥?/div>
Jitter attenuator can be disabled
鈥?/div>
Available in a 64 pin LQFP package.
鈥?/div>
Single 3.3V or 5.0V supply.
鈥?/div>
Operates over - 40
擄
C to 85
擄
C temperature range.
APPLICATIONS
鈥?/div>
E3/DS3 Access Equipment.
鈥?/div>
STS-SPE to DS3 Mapper
鈥?/div>
DSLAMs
MCLK_n
Timing Control Block
Phase locked Loop
ICT
DJA_n
RClk_n
RClkES
RPOS_n
RNEG_n
FSS
Write Clock
Read Clock
STS1_n
DS3/E3_n
RRCLK_n
RRPOS_n
16/32 Bit FIFO
RRNEG_n
FL_n
RRCLKES
Channel 0
Channel 1
Channel 2
MODE_CTRL
HOST
Reset
Microprocessor Serial
Interface
XRT71D03
n = 0, 1, 2
CS
SDI
SDO SClk
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
鈥?/div>
(510) 668-7000
鈥?/div>
FAX (510) 668-7017
鈥?/div>
www.exar.com

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