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XRT56L85D Datasheet

  • XRT56L85D

  • Line Interface

  • 12頁

  • ETC

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Low Power
PCM Line Interface
October 2000-1
XRT56L85
FEATURES
D
Low Power (Typical 14mA)
D
Single +5V Supply
D
Up to 2.048 Mbps Operation in Both TX and RX
Directions
D
Receiver Input can be:
Balanced Transformer Coupled
Capacitively (Twisted Pair)
Single Coaxial Capacitive Coupling
APPLICATIONS
D
T1 and CEPT Interfaces
D
CPI
D
DMI
GENERAL DESCRIPTION
The XRT56L85 is a PCM line interface chip. It consists of
both transmit and receive circuitry in a DIL 18 pin
package. The maximum bit rate the chip can handle is
2.048 Mbps and the signal level to the received can be
ORDERING INFORMATION
Part No.
XRT56L85P
XRT56L85D
attenuated by 10dB of cable loss at half the bit rate. Total
current consumption is between 12-16mA at +5V.
Package
18 Lead 300 Mil PDIP
18 Lead 300 Mil JEDEC SOIC
Operating
Temperature Range
-40擄C to +85擄C
擄
擄
-40擄C to +85擄C
擄
擄
BLOCK DIAGRAM
PDC
1
Positive
Threshold
Comparator
+
鈭?/div>
Negative
Threshold
Comparator
鈭?/div>
+
TTL Buffer
11 RPOS
TTL Buffer
8
4
RCLK
TE
RXDATA+ 2
RXDATA- 3
Peak
Detector
TTL Buffer
10 RNEG
6
TANK BIAS
Bias
RXV
CC
9
RXGND 7
TXV
CC
18
TPOS 17
TCLK 16
TNEG 12
TXGND 14
Bias
TTL Buffer
5
BIAS
15 TXDATA+
TTL Buffer
13 TXDATA-
Figure 1. Block Diagram
Rev. 2.11
E2000
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538
z
(510) 668-7000
z
FAX (510) 668-7017
1

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