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XR16L2552IM Datasheet

  • XR16L2552IM

  • 2.25V TO 5.5V DUART WITH 16-BYTE FIFO

  • 47頁(yè)

  • EXAR   EXAR

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xr
MAY 2005
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
GENERAL DESCRIPTION
The XR16L2552 (L2552) is a dual universal
asynchronous receiver and transmitter (UART) with 5
volt tolerant inputs. The XR16L2552 is an improved
version of the ST16C2552 UART with lower operating
voltages and 5 volt tolerant inputs. The L2552
provides enhanced UART functions with 16 byte TX
and RX FIFOs, automatic hardware (RTS/CTS) and
software (Xon/Xoff) flow control, and a complete
modem control interface. Onboard status registers
provide the user with error indications and
operational status. Indepedendent programmable
baud rate generators are provided to select transmit
and receive clock rates up to 3.125Mbps. An internal
loop-back capability allows onboard diagnostics. The
L2552 provides block mode data transfers (DMA)
through FIFO controls. DMA transfer monitoring is
provided through the signals TXRDY# and RXRDY#.
An Alternate Function Register provides the user with
the ability to write the control registers for both UARTs
concurrently and selection of the Multi-Function
output (Baudout#, OP2#, or RXRDY#).
N
OTE
:
1 Covered by U.S. Patent #5,649,122.
FEATURES
鈥?/div>
2.25 to 5.5 Volt Operation
鈥?/div>
5 Volt Tolerant Inputs
鈥?/div>
Pin-to-pin and functionally compatible to National
PC16552
鈥?/div>
Pin-to-pin Compatible to Exar鈥檚 ST16C2552,
XR16L2752 and XR16C2852 in the 44-PLCC
鈥?/div>
2 Independent UART Channels
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
APPLICATIONS
鈥?/div>
Portable Appliances
鈥?/div>
Telecommunication Network Routers
鈥?/div>
Ethernet Network Routers
鈥?/div>
Cellular Data Devices
鈥?/div>
Factory Automation and Process Controls
F
IGURE
1. XR16L2552 B
LOCK
D
IAGRAM
Up to 3.125Mbps with external clock of 50 MHz
Register Set Compatible to 16C550
16 byte Transmit FIFO to reduce the bandwidth
requirement of the external CPU
16 byte Receive FIFO with error tags to reduce
the bandwidth requirement of the external CPU
4 selectable RX FIFO Trigger Levels
Automatic RTS/CTS hardware flow control
Automatic XonXoff software flow control
Wireless infrared encoder/decoder
Full Modem Interface (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
Programmable character lengths (5, 6, 7, 8)
with even, odd, or no parity
Multi-Function output allows more package
functions with fewer I/O pins
鈥?/div>
Concurrent write to Channels A and B
鈥?/div>
Crystal oscillator or external clock input
鈥?/div>
48-TQFP (7x7x1.0 mm)
and 44-PLCC packages
A2:A0
D7:D0
IOR#
IOW#
CS#
CHSEL
INTA
INTB
TXRDY# A/B
RXRDY# A/B
(48-TQFP Only)
* 5 Volt Tolerant Inputs
UART Channel A
UART
Regs
BRG
8-bit Data
Bus
Interface
16 Byte TX FIFO
TX & RX
16 Byte RX FIFO
2.25 to 5.5 Volt VCC
GND
TXA
RXA
TXB
RXB
XTAL1
XTAL2
CTS#A/B, RI#A/B,
CD#A/B, DSR#A/B
DTR#A/B, RTS#A/B
2552BLK
UART Channel B
(same as Channel A)
MFA#
(OP2A#,
BAUDOUTA#, or
RXRDYA#)
Crystal Osc/Buffer
Modem Control Logic
MFB#
(OP2B#,
BAUDOUTB#, or
RXRDYB#)
Reset
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
鈥?/div>
(510) 668-7000
鈥?/div>
FAX (510) 668-7017
鈥?/div>
www.exar.com

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