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XQR4000XL Datasheet

  • XQR4000XL

  • QPRO XQR4000XL Radiation Hardened FPGAs

  • 197.87KB

  • 20頁(yè)

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0
R
QPRO XQR4000XL Radiation
Hardened FPGAs
0
2
DS071 (v1.1) June 25, 2000
Product Specification
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Systems-oriented features
- IEEE 1149.1-compatible boundary scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA sink current per output
Configured by loading binary file
- Unlimited reprogrammability
Readback capability
- Program verification
- Internal node observability
Development system runs on most common computer
platforms
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
Highest capacity: over 130,000 usable gates
Buffered interconnect for maximum speed
New latch capability in configurable logic blocks
Improved VersaRing鈩?I/O interconnect for better fixed
pinout flexibility
- Virtually unlimited number of clock signals
Optional multiplexer or 2-input function generator on
device outputs
5V tolerant I/Os
Advanced 0.35碌 process
Processed on Xilinx QML line
XQR4000XL Series Features
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Radiation-hardened FPGAs for space and satellite
applications
Guaranteed total ionizing dose
Latch-up immune
Low soft upset rate
Guaranteed to meet full electrical specifications over
鈥?5擄C to +125擄C
Available in -3 speed
System featured FPGAs
- SelectRAM鈩?memory: on-chip ultra-fast RAM with
路
synchronous write option
路
dual-port RAM option
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
networks
System performance beyond 60 MHz
Flexible array architecture
Low power segmented routing architecture
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Table 1:
XQR4000XL Series Radiation Hardened Field Programmable Gate Arrays
Max.
Logic
Gates
(No RAM)
13,000
36,000
62,000
Max. RAM
Bits
(No Logic)
18,432
41,472
73,728
Typical
Gate Range
(Logic and
RAM)
(1)
10,000 - 30,000
22,000 - 65,000
40,000 - 130,000
Number
of
Flip-Flops
1,536
3,168
5,376
Max.
User
I/O
192
288
384
Device
XQR4013XL
XQR4036XL
XQR4062XL
Logic
Cells
1,368
3,078
5,472
CLB
Matrix
24 x 24
36 x 36
48 x 48
Total
CLBs
576
1,296
2,304
Packages
CB228
CB228
CB228
Notes:
1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
漏 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS071 (v1.1) June 25, 2000
Product Specification
This Material Copyrighted by Its Respective Manufacturer
www.xilinx.com
1-800-255-7778
1

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