Advance Information
MPC755EC/D
Rev. 5, 6/2002
MPC755 RISC
Microprocessor
Hardware Specifications
This document is primarily concerned with the MPC755; however, unless otherwise noted, all
information here also applies to the MPC745. The MPC755 and MPC745 are reduced
instruction set computing (RISC) microprocessors that implement the PowerPC instruction
set architecture. This document describes pertinent physical characteristics of the MPC755.
For functional characteristics of the processor, refer to the
MPC750 RISC Microprocessor
Family User鈥檚 Manual.
This document contains the following topics:
Topic
Section 1.1, 鈥淥verview鈥?/span>
Section 1.2, 鈥淔eatures鈥?/span>
Section 1.3, 鈥淕eneral Parameters鈥?/span>
Section 1.4, 鈥淓lectrical and Thermal Characteristics鈥?/span>
Section 1.5, 鈥淧in Assignments鈥?/span>
Section 1.6, 鈥淧inout Listings鈥?/span>
Section 1.7, 鈥淧ackage Description鈥?/span>
Section 1.8, 鈥淪ystem Design Information鈥?/span>
Section 1.9, 鈥淒ocument Revision History鈥?/span>
Section 1.10, 鈥淥rdering Information鈥?/span>
Page
1
3
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33
46
48
To locate any published errata or updates for this document, refer to the website at
http://www.motorola.com/semiconductors.
1.1
Overview
The MPC755 is targeted for low-cost, low-power systems and supports the following power
management features鈥攄oze, nap, sleep, and dynamic power management. The MPC755
consists of a processor core and an internal L2 tag combined with a dedicated L2 cache
interface and a 60x bus. The MPC745 is identical to the MPC755 except it does not support
the L2 cache interface.
Figure 1 shows a block diagram of the MPC755.