Fact Sheet
MPC755
AND MPC745
MICROPROCESSORS
MPC755 and MPC745 microprocessors are high-performance, low-power, 32-bit
implementations of the PowerPC architecture, specially enhanced for embedded
applications. MPC755 and MPC745 microprocessors differ only in that the MPC755
features an enhanced, dedicated L2 cache interface with on-chip L2 tags. The MPC755
is a drop-in replacement for the award-winning MPC750 microprocessor and is
footprint- and user software code-compatible with the MPC7400 microprocessor with
AltiVec鈩?technology. The MPC745 is a drop-in replacement for the MPC740
microprocessor and is also footprint- and user software code-compatible with Motorola
G2 microprocessors. MPC755/MPC745 microprocessors provide on-chip debug support
and are fully JTAG-compliant.
SUPERSCALAR MICROPROCESSOR
MPC755 and MPC745 microprocessors are superscalar,
capable of issuing three instructions per clock cycle (two
instructions + branch) into six independent execution units:
鈥?Two integer units
鈥?Load/store unit
鈥?Double-precision floating-point unit
鈥?System register unit
鈥?Branch processing unit
MOTOROLA MPC755/MPC745 BLOCK DIAGRAM
Completion
Unit
Dispatch
Unit
Branch
Unit
Integer
Unit
Gen
Gen
Reg Rename
File
D MMU
Data Cache
Load/
Store
Unit
FPU
Reg
File
Floating
Point
Unit
I MMU
Inst. Cache
Bus Interface Unit
L2 Tags
L2 Cache
Port (755 only)
FSRAM
32-bit Address
32-/64-bit Data
System Bus
1
2
