鈥?/div>
Enhancement MOS FET
Unit: mm
For switching
2.8
-0.3
0.65鹵0.15
+0.2
+0.25
1.5
-0.05
5
0.65鹵0.15
1
0.95
2.9
-0.05
q
q
Two elements incorporated into one package.
(Source-coupled FETs)
Reduction of the mounting area and assembly cost by one half.
1.9鹵0.1
+0.2
4
0.95
3
2
0.3
-0.05
0.4鹵0.2
0.16
-0.06
+0.1
1.1
-0.1
q
2SK621
脳
2 elements
0.8
s
Basic Part Number of Element
+0.2
s
Absolute Maximum Ratings
Parameter
Drain to source voltage
Rating Gate to source voltage
of
element
Drain current
Total power dissipation
Overall Channel temperature
Storage temperature
Symbol
V
DSS
V
GSO
I
D
I
DM
P
T
T
ch
T
stg
(Ta=25藲C)
Ratings
50
8
100
200
300
150
鈥?5 to +150
Unit
V
V
mA
mA
mW
藲C
藲C
1 : Drain (Tr1)
2 : Drain (Tr2)
3 : Gate (Tr2)
0 to 0.1
0.1 to 0.3
4 : Source
5 : Gate (Tr1)
EIAJ : SC鈥?4A
Mini Type Pakage (5鈥損in)
Marking Symbol:
5U
Internal Connection
5
4
3
2
FET 1
1
FET 2
s
Electrical Characteristics
Parameter
Drain to source voltage
Drain current
Gate cutoff current
Gate threshold voltage
Drain resistance
Forward transfer admittance
Output voltage high level
Output voltage low level
Input resistance
Turn-on time
Turn-off time
Common source short-circuit input capacitance
*1
*2
(Ta=25藲C)
Symbol
V
DSS
I
DSS
I
GSS
V
th
R
DS(on)
| Y
fs
|
V
OH
V
OL
R
1
+R
2*1
t
on*2
t
off*2
C
iss
V
DD
= 5V, V
GS
= 0 to 5V, R
L
= 200鈩?/div>
V
DD
= 5V, V
GS
= 5 to 0V, R
L
= 200鈩?/div>
V
DS
= 5V, V
GS
= 0, f = 1MHz
9
Conditions
I
D
= 100碌A, V
GS
= 0
V
DS
= 10V, V
GS
= 0
V
GS
= 8V, V
DS
= 0
I
D
= 100碌A, V
DS
= V
GS
I
D
= 20mA, V
GS
= 5V
I
D
= 20mA, V
DS
= 5V, f = 1kHz
V
DS
= 5V, V
GS
= 1V, R
L
= 200鈩?/div>
V
DS
= 5V, V
GS
= 5V, R
L
= 200鈩?/div>
100
20
4.5
1.0
200
1.0
1.0
15
30
40
1.5
min
50
10
80
3.5
50
typ
max
Unit
V
碌A
碌A
V
鈩?/div>
mS
V
V
k鈩?/div>
碌s
碌s
pF
Pulse measurement
Resistance ratio R
1
/R
2
= 1/50
+0.1
1.45鹵0.1
s
Features
1
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