鈥?/div>
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25
o
C unless otherwise specified)
Drain-Source and Gate-Source Voltage . . . . . . . . . . . . . . 25V
Peak Gate-Source Voltage (Note 1) . . . . . . . . . . . . . . .
鹵125V
Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Storage Temperature Range . . . . . . . . . . . . . -65
o
C to +200
o
C
Operating Temperature Range . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . +300
o
C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375mW
Derate above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . 3mW/
o
C
NOTE:
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
TO-72
ORDERING INFORMATION
Part
D
C
G
S
Package
Hermetic TO-72
Sorted Chips in Carriers
Temperature Range
-55
o
C to +150
o
C
-55
o
C to +150
o
C
IT1750
XIT1750
1003
ELECTRICAL CHARACTERISTICS
(T
A
= 25
o
C, Body connected to Source and V
BS
= 0 unless otherwise specified)
SYMBOL
V
GS(th)
I
DSS
I
GSS
BV
DSS
r
DS(on)
I
D(on)
Y
fs
C
iss
C
dg
PARAMETER
Gate to Source Threshold Voltage
Drain Leakage Current
Gate Leakage Current
Drain Breakdown Voltage
Drain to Source on Resistance
Drain Current
Forward Transadmittance
Total Gate Input Capacitance
Gate to Drain Capacitance
10
3,000
6.0
1.6
25
50
MIN
0.50
MAX
3.0
10
(See note 2)
V
ohms
mA
碌S
pF
pF
I
D
= 10碌A(chǔ), V
GS
= 0
V
GS
= 20V
V
DS
= V
GS
=10V
V
DS
= 10V, I
D
= 10mA, f = 1kHz
I
D
= 10mA, V
DS
= 10V, f = 1MHz (Note 3)
V
DG
= 10V, f = 1MHz (Note 3)
UNITS
V
nA
TEST CONDITIONS
V
DS
= V
GS
, I
D
= 10碌A(chǔ)
V
DS
= 10V, V
GS
= 0
NOTES: 1.
Devices must not be tested at
鹵125V
more than once nor longer than 300ms.
2.
Actual gate current is immeasurable. Package suppliers are required to guarantee a package leakage of < 10pA.
External package leakage is the dominant mode which is sensitive to both transient and storage environment, which cannot be guaranteed.
3.
For design reference only, not 100% tested.
CALOGIC
1
