鈥?/div>
Supports Pentium芒 and Pentium芒Pro and Mobil
Pentium芒 Processor designs.
4 CPU clocks up to 8 loads.
Up to 8 SDRAM clocks for 2 DIMMs.
Supports Power Management.
7 PCI synchronous clocks.
Optional common or mixed supply mode:
(Vdd = Vddq3 = Vddq2 = 3.3V) or
(Vdd = Vddq3 = 3.3V, Vddq2 = 2.5V)
< 250ps skew CPU and SDRAM clocks.
< 250ps skew among PCI clocks.
SMBUS 2-Wire serial interface
Programmable registers featuring:
enable/disable each output pin
mode as tri-state, test, or normal
24/48 MHz selections
1 IOAPIC clock for multiprocessor support.
48-pin SSOP and TSSOP package
Spread Spectrum
Technology for up to 13dB of
EMI reduction
Frequency Table
SEL
0
CPU
60.0
PCI
30.0
33.3*
1
66.6*
*Spread Spectrum mode capable
Pin Configuration
XG571
REF1
REF0
Vss
Xin
Xout
MODE
Vddq3
PCICLK_F
PCICLK0
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Vdd
REF2
Vddq2
IOAPIC0
PW R_DW N#
Vss
CPUCLK0
CPUCLK1
Vddq2
CPUCLK2
CPUCLK3
Vss
SDRAM0
SDRAM 1
Vddq3
SDRAM 2
SDRAM 3
Vss
SDRAM 4
SDRAM 5
Vddq3
SDRAM6/CPU_STOP#
SDRAM7/PCI_STOP#
Vdd
Block Diagram
Buffers
Xin
Xout
REF
OSC
Vddq2
IOAPIC0
Buffer
SDATA
SDCLK
Vddq2
4
Buffers
Vddq3
8
Buffers
6
Buffers
PCI_STOP#
CPU_STOP#
PWR_DWN#
MODE
PCICLK_F
Buffer
SDRAM0~7
PCICLK0~5
CPUCLK0~3
3
REF0,1,2
PCICLK1
PCICLK2
PCICLK3
PCICLK4
Vddq3
PCICLK5
Vss
SEL
SDATA
SDCLK
Vddq3
48/24MHZ
Buffer
48/24MHZ
SEL
PLL1
dly
48/24MHZ
Vss
PLL2
Buffer
48/24MHZ
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07019 Rev. **
5/17/2001
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