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XF-HDLC Datasheet

  • XF-HDLC

  • Controller Miscellaneous - Datasheet Reference

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  • 6頁

  • ETC

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Single-Channel XF-HDLC
Controller
February 14, 2000
Product Speci鏗乧ation
AllianceCORE
鈩?/div>
Facts
Core Speci鏗乧s
See Table 1
Provided with Core
7810 South Hardy Drive, Suite 104
Tempe, Arizona 85284 USA
Phone: +1 888-845-5585 (USA)
+1 480-753-5585
Fax:
+1 480-753-5899
E-mail: info@memecdesign.com
URL:
www.memecdesign.com
Documentation
User鈥檚 guide
Design File Formats
Verilog source RTL
1
Constraint Files
hdlc.ucf
Verification
Verilog Testbench, test vectors
Instatiation Templates
VHDL, Verilog
Reference Designs
Application Note
and Application Notes
Additional Items
None
Simulation Tool Used
Silos III
Support
Support provided by Memec Design Services
Notes:
1. Synplify 5.08A used for synthesis
Features
鈥?Supports 4000X, Spartan, Virtex鈩? Virtex鈩?E, and
Spartan鈩?II devices.
鈥?Conforms to International Standard ISO/IEC 3309
Speci鏗乧ation
鈥?Starting point for a custom design
鈥?16-bit/32-bit CCITT-CRC generation and checking
鈥?Flag & Zero insertion and detection
鈥?Full Duplex Operation allowed
鈥?DC to 53 Mbps (STS-1) data rate
鈥?Full synchronous operation
鈥?Interface can be customized for user FIFO and DMA
requirements
Applications
鈥?Frame Relay, ISDN and X.25 protocols
鈥?Logic consolidation
Table 1: Core Implementation Data
CLBs
2
Core+
Core
Ext logic
183
2
183
2
183
2
183
2
183
2
183
2
127
127
134
134
Clock
IOBs
2
2
2
2
2
IOBs
1
Core+
Core
Ext logic
32
32
32
32
32
32
32
32
32
32
Performance
3
(MHz)
77
90
79
53
57
Supported
Family
Spartan-II
Virtex-E
Virtex
Spartan
4000X
Device
Tested
2S15-5
V50E-6
V50-4
S10-4
4005XL-2
Xilinx
Tools
M2.1i
M2.1i
M2.1i
M1.5i
M1.5i
Special
Features
None
None
None
None
None
Notes:
1. Assuming all core I/Os are routed off-chip.
2. Utilization numbers for Virtex, Virtex-E, and Spartan-II, are in CLB slices.
3. Minimum guaranteed speed
February 14, 2000
3-1

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  • 英文版
    Controller Miscellaneous - Datasheet Reference
    ETC
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    Controller Miscellaneous - Datasheet Reference

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