鈥?/div>
Lowest power 384 macrocell CPLD
7.5 ns pin-to-pin logic delays
System frequencies up to 127 MHz
384 macrocells with 9,000 usable gates
Available in small footprint packages
- 144-pin TQFP (118 user I/O)
- 208-pin PQFP (172 user I/O)
- 256-ball FBGA (212 user I/O)
- 324-ball FBGA (220 user I/O)
Optimized for 3.3V systems
- Ultra low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power鈩?(FZP) CMOS design
technology
Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 clocks available per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
Fast ISP programming times
Port Enable pin for additional I/O
2.7V to 3.6V supply voltage at industrial grade voltage
range
Programmable slew rate control per output
Security bit prevents unauthorized access
Refer to XPLA3 family data sheet (DS012) for
architecture description
Description
The XCR3384XL is a 3.3V, 384 macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of 24 function blocks provide
9,000 usable gates. Pin-to-pin propagation delays are
7.5 ns with a maximum system frequency of 127 MHz.
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1
and
Table 1
showing the I
CC
vs. Frequency of our
XCR3384XL TotalCMOS CPLD (data taken with 24
resetable up/down, 16-bit counters at 3.3V, 25擄C).
鈥?/div>
鈥?/div>
140
120
100
Typical ICC (mA)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
80
60
40
20
0
0
20
40
60
80
100
120
140
160
Frequency (MHz)
DS024_01_112700
Figure 1:
XCR3384XL Typical I
CC
vs. Frequency at
V
CC
= 3.3V, 25擄C
Table 1:
Typical I
CC
vs. Frequency at V
CC
= 3.3V, 25擄C
Frequency (MHz)
Typical I
CC
(mA)
0
TBD
1
TBD
10
TBD
20
TBD
40
TBD
60
TBD
80
TBD
100
TBD
120
TBD
140
TBD
漏 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS024 (v1.4) January 8, 2002
Advance Product Specification
www.xilinx.com
1-800-255-7778
1
XCR3384XLSERIES相關(guān)型號(hào)PDF文件下載
-
型號(hào)
版本
描述
廠商
下載
-
英文版
32 Macrocell CPLD
XILINX [Xi...
-
英文版
Product Specification
-
英文版
Product Specification
-
英文版
Product Specification
-
英文版
Product Specification
-
英文版
with Enhanced Clocking
-
英文版
64 Macrocell CPLD With Enhanced Clocking
XILINX [Xi...
-
英文版
CPLD with Enhanced Clocking
-
英文版
CPLD with Enhanced Clocking
XILINX [Xi...
-
英文版
XCR3032XL 32 Macrocell CPLD
-
英文版
XCR3032XL 32 Macrocell CPLD
XILINX [Xi...
-
英文版
XCR3064XL 64 Macrocell CPLD
-
英文版
XCR3064XL 64 Macrocell CPLD
XILINX [Xi...
-
英文版
XCR3128XL 128 Macrocell CPLD
-
英文版
XCR3128XL 128 Macrocell CPLD
XILINX [Xi...
-
英文版
256 Macrocell CPLD
-
英文版
256 Macrocell CPLD
XILINX [Xi...
-
英文版
256 Macrocell CPLD
XILINX [Xi...
-
英文版
384 Macrocell CPLD
-
英文版
384 Macrocell CPLD
XILINX [Xi...
1
2
3
4
5
6
7
8
9
10
11
12
