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XCR3064XL Datasheet

  • XCR3064XL

  • XCR3064XL 64 Macrocell CPLD

  • 9頁

  • XILINX   XILINX

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XCR3064XL 64 Macrocell CPLD
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DS017 (v1.1) August 30, 2000
Preliminary Product Specification
Features
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6.0 ns pin-to-pin logic delays
System frequencies up to 145 MHz
64 macrocells with 1,500 usable gates
Available in small footprint packages
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44-pin VQFP (36 user I/O pins)
48-ball CS BGA (40 user I/O pins)
56-ball CP BGA (48 user I/O pins)
100-pin TQFP (68 user I/O pins)
Ultra-low power operation
5V tolerant I/O pins with 3.3V core supply
Advanced 0.35 micron five metal layer
reprogrammable process
FZP鈩?CMOS design technology
In-system programming
Input registers
Predictable timing model
Up to 23 available clocks per logic block
Excellent pin retention during design changes
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Four global clocks
Eight product term control terms per logic block
Description
The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of four logic blocks provide
1,500 usable gates. Pin-to-pin propagation delays are
6.0 ns with a maximum system frequency of 145 MHz.
TotalCMOS鈩?Design Technique for
Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1
and
Table 1
showing the I
CC
vs. Frequency of our
XCR3064XL TotalCMOS CPLD (data taken with four
up/down, loadable 16-bit counters at 3.3V, 25擄C).
Optimized for 3.3V systems
Advanced system features
Fast ISP programming times
Port Enable pin for dual function of JTAG ISP pins
2.7V to 3.6V industrial temperature range
Programmable slew rate control per macrocell
Security bit prevents unauthorized access
Refer to XPLA3 family data sheet (DS012) for
architecture description
漏 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners.
All specifications are subject to change without notice.
DS017 (v1.1) August 30, 2000
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
1

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