鈥?/div>
44-pin PLCC (36 user I/O pins)
44-pin VQFP (36 user I/O pins)
48-ball CS BGA (40 user I/O pins)
56-ball CP BGA (48 user I/O pins)
100-pin VQFP (68 user I/O pins)
Ultra-low power operation
5V tolerant I/O pins with 3.3V core supply
Advanced 0.35 micron five layer metal EEPROM
process
Fast Zero Power鈩?(FZP) CMOS design
technology
In-system programming
Predictable timing model
Up to 23 available clocks per function block
Excellent pin retention during design changes
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Four global clocks
Eight product term control terms per function block
Description
The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of four function blocks provide
1,500 usable gates. Pin-to-pin propagation delays are
6.0 ns with a maximum system frequency of 145 MHz.
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1
and
Table 1
showing the I
CC
vs. Frequency of our
XCR3064XL TotalCMOS CPLD (data taken with four
resetable up/down, 16-bit counters at 3.3V, 25擄C).
35.0
30.0
Optimized for 3.3V systems
Advanced system features
-
-
-
-
-
-
-
-
Input registers
Typical I
CC
(mA)
25.0
20.0
15.0
10.0
5.0
0.0
0
20
40
60
80
100
120
140
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Fast ISP programming times
Port Enable pin for dual function of JTAG ISP pins
2.7V to 3.6V supply voltage at industrial temperature
range
Programmable slew rate control per macrocell
Security bit prevents unauthorized access
Refer to XPLA3 family data sheet (DS012) for
architecture description
Frequency (MHz)
DS017_01_102401
Figure 1:
I
CC
vs. Frequency at V
CC
= 3.3V, 25擄C
Table 1:
I
CC
vs. Frequency
(V
CC
= 3.3V, 25擄C)
Frequency (MHz)
Typical I
CC
(mA)
0
0
1
0.2
5
1.0
10
2.0
20
3.9
40
7.6
60
11.3
80
14.8
100
18.5
120
22.1
140
25.6
漏 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS017 (v1.6) January 8, 2002
Product Specification
www.xilinx.com
1-800-255-7778
1
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