鈥?/div>
Lowest power 32 macrocell CPLD
5.0 ns pin-to-pin logic delays
System frequencies up to 200 MHz
32 macrocells with 750 usable gates
Available in small footprint packages
- 48-ball CS BGA (36 user I/O pins)
- 44-pin VQFP (36 user I/O)
- 44-pin PLCC (36 user I/O)
Optimized for 3.3V systems
- Ultra-low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power鈩?(FZP) CMOS design
technology
Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
Fast ISP programming times
Port Enable pin for dual function of JTAG ISP pins
2.7V to 3.6V supply voltage at industrial temperature
range
Programmable slew rate control per macrocell
Security bit prevents unauthorized access
Refer to XPLA3 family data sheet (DS012) for
architecture description
Description
The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of two function blocks provide
750 usable gates. Pin-to-pin propagation delays are 5.0 ns
with a maximum system frequency of 200 MHz.
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1
and
Table 1
showing the I
CC
vs. Frequency of our
XCR3032XL TotalCMOS CPLD (data taken with two
resetable up/down, 16-bit counters at 3.3V, 25擄C).
20
鈥?/div>
鈥?/div>
Typical I
CC
(mA)
15
10
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鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
5
0
0
20
40
60
80
100
120
140
160
180
200
Frequency (MHz)
DS023_01_080101
Figure 1:
I
CC
vs. Frequency at V
CC
= 3.3V, 25擄C
Table 1:
I
CC
vs. Frequency
(V
CC
= 3.3V, 25擄C)
Frequency (MHz)
Typical I
CC
(mA)
0
0.02
1
0.13
5
0.54
10
1.06
20
2.09
50
5.2
100
10.26
200
20.3
漏 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS023 (v1.5) January 8, 2002
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
1
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