鈥?/div>
72 macrocells with 1,600 usable gates
Available in small footprint packages
- 44-pin PLCC (34 user I/O pins)
- 44-pin VQFP (34 user I/O pins)
- 48-pin CSP (38 user I/O pins)
- 100-pin TQFP (72-user I/O pins)
Optimized for high-performance 2.5V systems
- Low power operation
- Multi-voltage operation
Advanced system features
- In-system programmable
- Two separate output banks
- Superior pin-locking and routability with
FastCONNECT II鈩?switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold ciruitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I
CC
, the following equation may be
used:
I
CC
(mA) =
MC
HP
(0.36) + MC
LP
(0.23) + MC(0.005 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance (default) mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual I
CC
value varies
with the design application and should be verified during
normal system operation.
Figure 1
shows the above estimation in a graphical form.
90
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
70
Typical I
CC
(mA)
for
P er
P
Low
ma
nce
50
30
Hig
h
ow
er
10
Description
The XC9572XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of four
54V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 4 ns.
0
50
100
150
Clock Frequency (MHz)
200
DS052_01_012501
Figure 1:
Typical I
CC
vs. Frequency for XC9572XV
漏 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS052 (v2.2) August 27, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
1
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