鈥?/div>
5 ns pin-to-pin logic delays
System frequency up to 178 MHz
144 macrocells with 3,200 usable gates
Available in small footprint packages
- 100-pin TQFP (81 user I/O pins)
- 144-pin TQFP (117 user I/O pins)
- 144-pin CSP (117 user I/O pins)
Optimized for high-performance 3.3 V systems
- Low power operation
- 5 V tolerant I/O pins accept 5 V, 3.3 V, and 2.5 V
signals
- 3.3 V or 2.5 V output capability
- Advanced 0.35 micron feature size CMOS
FastFLASH鈩?technology
Advanced system features
- In-system programmable
- Superior pin-locking and routability with
FastCONNECT II鈩?switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with individual
product-term allocation
- Local clock inversion with 3 global and one product-
term clocks
- Individual output enable per output pin with local
inversion
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold ciruitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
- Endurance exceeding 10,000 program/erase cycles
- 20 year data retention
- ESD protection exceeding 2,000 V
Pin-compatible with 5 V-core XC95144 device in the
100-pin TQFP package
Power Estimation
Power dissipation in CPLDs can very substantially depend-
ing on the system frequency, design application, and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I
CC
, the following equation may
be used:
I
CC
(mA) = MC
HP
(0.5) + MC
LP
(0.3) + MC(0.0045 mA/MHz) f
鈥?/div>
Where:
MC
HP
= Macrocells in high-performance (default) mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual I
CC
value varies
with the design application and should be verified during
normal system operation.
Figure 1 shows the above estimation in graphical form.
鈥?/div>
200
e
anc
orm
f
Per
igh
H
104 MHz
178 MHz
Typical I
CC
(mA)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
150
100
P
Low
owe
r
50
鈥?/div>
Description
The XC95144XL is a 3.3 V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of eight
54V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 5 ns. See Figure 2 for architecture
overview.
0
50
150
100
Clock Frequency (MHz)
200
X5898C
Figure 1: Typical I
cc
vs. Frequency for XC95144XL
November 13, 1998 (Version 1.2)
1
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