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XC9500 Datasheet

  • XC9500

  • XC9500 In-System Programmable CPLD Family

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k
0
R
XC9500 In-System Programmable
CPLD Family
0
0
DS063 (v5.1) September 22, 2003
Product Specification
-
-
Advanced CMOS 5V Fast FLASH鈩?technology
Supports parallel programming of multiple XC9500
devices
Features
鈥?/div>
High-performance
-
-
鈥?/div>
-
鈥?/div>
5 ns pin-to-pin logic delays on all pins
f
CNT
to 125 MHz
36 to 288 macrocells with 800 to 6,400 usable
gates
Endurance of 10,000 program/erase cycles
Program/erase over full commercial voltage and
temperature range
Family Overview
The XC9500 CPLD family provides advanced in-system
programming and test capabilities for high performance,
general purpose logic integration. All devices are in-system
programmable for a minimum of 10,000 program/erase
cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan sup-
port is also included on all family members.
As shown in
Table 1,
logic density of the XC9500 devices
ranges from 800 to over 6,400 usable gates with 36 to 288
registers, respectively. Multiple package options and asso-
ciated I/O capacity are shown in
Table 2.
The XC9500 fam-
ily is fully pin-compatible allowing easy design migration
across multiple density options in a given package footprint.
The XC9500 architectural features address the require-
ments of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. An expanded JTAG
instruction set allows version control of programming pat-
terns and in-system debugging. In-system programming
throughout the full device operating range and a minimum
of 10,000 program/erase cycles provide worry-free recon-
figurations and system field upgrades.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
noise. I/Os may be configured for 3.3V or 5V operation. All
outputs provide 24 mA drive.
Large density range
5V in-system programmable
-
-
鈥?/div>
鈥?/div>
Enhanced pin-locking architecture
Flexible 36V18 Function Block
-
-
-
-
-
-
-
-
-
90 product terms drive any or all of 18 macrocells
within Function Block
Global and product term clocks, output enables,
set and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design
protection
High-drive 24 mA outputs
3.3V or 5V I/O capability
Table 1:
XC9500 Device Family
XC9536
Macrocells
Usable Gates
Registers
T
PD
(ns)
T
SU
(ns)
T
CO
(ns)
f
CNT
(MHz)
(1)
f
SYSTEM
(MHz)
(2)
36
800
36
5
3.5
4.0
100
100
XC9572
72
1,600
72
7.5
4.5
4.5
125
83.3
XC95108
108
2,400
108
7.5
4.5
4.5
125
83.3
XC95144
144
3,200
144
7.5
4.5
4.5
125
83.3
XC95216
216
4,800
216
10
6.0
6.0
111.1
66.7
XC95288
288
6,400
288
15
8.0
8.0
92.2
56.6
Notes:
1. f
CNT
= Operating frequency for 16-bit counters.
2. f
SYSTEM
= Internal operating frequency for general purpose system designs spanning multiple FBs.
漏 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS063 (v5.1) September 22, 2003
Product Specification
www.xilinx.com
1-800-255-7778
1

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