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XC7354 Datasheet

  • XC7354

  • XC7300 CMOS EPLD Family

  • 10頁(yè)

  • XILINX   XILINX

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XC7300 CMOS EPLD Family
Product Description
Features
鈥?High-performance Erasable Programmable Logic
Devices (EPLDs)
鈥?5 / 7.5 ns pin-to-pin speeds on all fast inputs
鈥?Up to 167 MHz maximum clock frequency
鈥?Advanced Dual-Block architecture
鈥?Fast Function Blocks
鈥?High-Density Function Blocks
(XC7354, XC7372, XC73108, XC73144)
鈥?100% interconnect matrix
鈥?High-speed arithmetic carry network
鈥?1 ns ripple-carry delay per bit
鈥?43 to 61 MHz 18-bit accumulators
鈥?Multiple independent clocks
鈥?Each input programmable as direct, latched, or
registered
鈥?High-drive 24 mA output
鈥?I/O operation at 3.3 V or 5 V
鈥?Meets JEDEC Standard (8-1A) for 3.3 V
鹵
0.3 V
鈥?Power management options
鈥?Multiple security bits for design protection
鈥?Supported by industry standard design and verification
tools
鈥?100% PCI compliant
Description
The XC7300 family employs a unique Dual-Block architec-
ture, which provides high speed operations via Fast Func-
tion Blocks and/or high density capability via High Density
Function Blocks.
Fast Function Blocks (FFBs) provide fast, pin-to-pin
speed and logic throughput for critical decoding and ultra-
fast state machine applications. High-Density Function
Blocks (FBs) provide maximum logic density and system-
level features to implement complex functions with pre-
dictable timing for adders and accumulators, wide func-
tions and state machines requiring large numbers of
product terms, and other forms of complex logic.
In addition, the XC7300 architecture employs the Univer-
sal Interconnect Matrix (UIM) which guarantees 100%
interconnect of all internal functions. This interconnect
scheme provides constant, short interconnect delays for
all routing paths through the UIM. Constant interconnect
delays simplify device timing and guarantee design perfor-
mance, regardless of logic placement within the chip.
All XC7300 devices are designed in 0.8
碌
CMOS EPROM
technology.
All XC7300 EPLDs include programmable power manage-
ment features to specify high-performance or low-power
operation on an individual Macrocell-by-Macrocell basis.
Unused Macrocells are automatically turned off to mini-
The XC7300 Family
XC7318
Typical 22V10 Equivalent
Number of Macrocells
Number of Function Blocks
Number of Flip-Flops
Number of Fast Inputs
Number of Signal Pins
1.5 鈥?2
18
2
18
12
38
XC7336
3鈥?
36
4
36
12
38
XC7354
6
54
6
108
12
58
XC7372
8
72
8
126
12
84
XC73108
12
108
12
198
12
120
XC73144
16
144
16
276
12
156
2-1
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