音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

XC4005 Datasheet

  • XC4005

  • Logic Cell Array Family

  • 22頁

  • XILINX   XILINX

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

廬
XC4000
Logic Cell Array Family
Product Specifications
Features
Description
The XC4000 family of Field-Programmable Gate Arrays
(FPGAs) provides the benefits of custom CMOS VLSI,
while avoiding the initial cost, time delay, and inherent risk
of a conventional masked gate array.
The XC4000 family provides a regular, flexible, program-
mable architecture of Configurable Logic Blocks (CLBs),
interconnected by a powerful hierarchy of versatile routing
resources, and surrounded by a perimeter of program-
mable Input/Output Blocks (IOBs).
XC4000 devices have generous routing resources to ac-
commodate the most complex interconnect patterns. They
are customized by loading configuration data into the inter-
nal memory cells. The FPGA can either actively read its
configuration data out of external serial or byte-parallel
PROM (master modes), or the configuration data can be
written into the FPGA (slave and peripheral modes).
The XC4000 family is supported by powerful and sophisti-
cated software, covering every aspect of design: from
schematic entry, to simulation, to automatic block place-
ment and routing of interconnects, and finally the creation
of the configuration bit stream.
Since Xilinx FPGAs can be reprogrammed an unlimited
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hard-
ware must be adapted to different user applications. FPGAs
are ideal for shortening the design and development cycle,
but they also offer a cost-effective solution for production
rates well beyond 1000 systems per month.
For a detailed description of the device features, architec-
ture, configuration methods and pin descriptions, see
pages 2-9 through 2-45.
鈥?/div>
Third Generation Field-Programmable Gate Arrays
Abundant flip-flops
Flexible function generators
On-chip ultra-fast RAM
Dedicated high-speed carry-propagation circuit
Wide edge decoders (four per edge)
Hierarchy of interconnect lines
Internal 3-state bus capability
Eight global low-skew clock or signal distribution
network
鈥?/div>
Flexible Array Architecture
鈥?Programmable logic blocks and I/O blocks
鈥?Programmable interconnects and wide decoders
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Sub-micron CMOS Process
鈥?High-speed logic and Interconnect
鈥?Low power consumption
鈥?/div>
Systems-Oriented Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
IEEE 1149.1-compatible boundary-scan logic support
Programmable output slew rate (2 modes)
Programmable input pull-up or pull-down resistors
12-mA sink current per output
24-mA sink current per output pair
鈥?/div>
Configured by Loading Binary File
鈥?Unlimited reprogrammability
鈥?Six programming modes
鈥?/div>
XACT Development System runs on 鈥?86/鈥?86-type PC,
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700
series
鈥?Interfaces to popular design environments like
Viewlogic, Mentor Graphics and OrCAD
鈥?Fully automatic partitioning, placement and routing
鈥?Interactive design editor for design optimization
鈥?288 macros, 34 hard macros, RAM/ROM compiler
Table 1. The XC4000 Family of Field-Programmable Gate Arrays
Device
Appr. Gate Count
CLB Matrix
Number of CLBs
Number of Flip-Flops
Max Decode Inputs (per side)
Max RAM Bits
Number of IOBs
*XC4010D has no RAM
XC4003
3,000
10 x 10
100
360
30
3,200
80
XC4005
5,000
14 x 14
196
616
42
6,272
112
XC4006
6,000
16 x 16
256
768
48
8,192
128
XC4008 XC4010/10D
8,000
18 x 18
324
936
54
10,368
144
10,000
20 x 20
400
1,120
60
12,800*
160
XC4013
13,000
24 x 24
576
1,536
72
18,432
192
XC4020
20,000
28 x 28
784
2,016
84
25,088
224
XC4025
25,000
32 x 32
1,024
2,560
96
32,768
256
2-47

XC4005相關(guān)型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！