廬
XC3000A
Logic Cell Array Family
Product Specifications
Features
Description
The XC3000A family offers the following enhancements
over the popular XC3000 family:
The XC3000A family has additional interconnect resources
to drive the I-inputs of TBUFs driving horizontal Longlines.
The CLB Clock Enable input can be driven from a second
vertical Longline. These two additions result in more
efficient and faster designs when horizontal Longlines are
used for data bussing.
During configuration, the XC3000A devices check the
bitstream format for stop bits in the appropriate positions.
Any error terminates the configuration and pulls INIT Low.
When the configuration process is finished and the device
starts up in user mode, the first activation of the outputs is
automatically slew-rate limited . This feature, called Soft
Startup, avoids the potential ground bounce when all
outputs are turned on simultaneously. After start-up, the
slew rate of the individual outputs is, as in the XC3000
family, determined by the individual configuration option.
The XC3000A family is a superset of the XC3000 family.
Any bitstream used to configure an XC3000 or XC3100
device configures an XC3000A device exactly the same
way.
鈥?/div>
Enhanced, high performance FPGA family with five
device types
鈥?Improved redesign of the basic XC3000 LCA
Family
鈥?Logic densities from 1,000 to 6,000 gates
鈥?Up to 144 user-definable I/Os
鈥?/div>
Superset of the industry-leading XC3000 family
鈥?Identical to the basic XC3000 in structure, pin out,
design methodology, and software tools
鈥?100% compatible with all XC3000, XC3000L,
and XC3100 bitstreams
鈥?Improved routing and additional features
鈥?/div>
Additional programmable interconnection points
(PIPs)
鈥?Improved access to longlines and CLB clock
enable inputs
鈥?Most efficient XC3000-class solution to bus-ori-
ented designs
鈥?/div>
Advanced 0.8
碌
CMOS static memory technology
鈥?Low quiescent and active power consumption
鈥?/div>
Performance specified by logic delays, faster than
corresponding XC3000 versions
鈥?/div>
XC3000A-specific features
鈥?4 mA output sink and source current
鈥?Error checking of the configuration bitstream
鈥?Soft startup starts all outputs in slew-limited mode
upon power-up
鈥?Easy migration to the XC3400 series of HardWire
mask programmed devices for high-volume
production.
User I/Os
Max
64
80
96
120
144
Horizontal
Longlines
16
20
24
32
40
Configurable
Data Bits
14,779
22,176
30,784
46,064
64,160
Device
XC3020A
XC3030A
XC3042A
XC3064A
XC3090A
CLBs
64
100
144
224
320
Array
8x8
10 x 10
12 x 12
16 x 14
16 x 20
Flip-Flops
256
360
480
688
928
2-161
XC3030A相關(guān)型號PDF文件下載
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英文版
Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
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英文版
Logic Cell Array Families
XILINX [Xi...
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英文版
Field Programmable Gate Arrays (XC3000A/L, XC3...
XILINX [Xi...
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英文版
Logic Cell Array Families
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英文版
Logic Cell Array Families
XILINX [Xi...
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英文版
Logic Cell Array Families
-
英文版
Logic Cell Array Families
XILINX [Xi...
-
英文版
Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
-
英文版
Field Programmable Gate Arrays (XC3000A/L, XC3...
XILINX [Xi...
-
英文版
Logic Cell Array Families
XILINX [Xi...
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英文版
Logic Cell Array Families
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英文版
Logic Cell Array Families
XILINX [Xi...
-
英文版
Logic Cell Array Families
-
英文版
Logic Cell Array Families
XILINX [Xi...
-
英文版
Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
-
英文版
Logic Cell Array Families
XILINX [Xi...
-
英文版
Logic Cell Array Family
XILINX [Xi...
-
英文版
Field Programmable Gate Arrays (XC3000A/L, XC3...
XILINX [Xi...
-
英文版
Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
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英文版
Logic Cell Array Families
XILINX [Xi...
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